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//////////////////////////////////////////////////////////////////////
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///////////3///////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// tb_eth_top.v ////
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//// tb_eth_top.v ////
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//// ////
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//// ////
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//// This file is part of the Ethernet IP core project ////
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//// This file is part of the Ethernet IP core project ////
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//// http://www.opencores.org/cores/ethmac/ ////
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//// http://www.opencores.org/cores/ethmac/ ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.3 2001/09/24 14:55:49 mohor
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// Defines changed (All precede with ETH_). Small changes because some
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// tools generate warnings when two operands are together. Synchronization
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// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
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// demands).
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//
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// Revision 1.2 2001/08/15 14:04:30 mohor
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// Revision 1.2 2001/08/15 14:04:30 mohor
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// Signal names changed on the top level for easier pad insertion (ASIC).
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// Signal names changed on the top level for easier pad insertion (ASIC).
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//
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//
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// Revision 1.1 2001/08/06 14:41:09 mohor
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// Revision 1.1 2001/08/06 14:41:09 mohor
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// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
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// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
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//
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//
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`include "eth_defines.v"
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`include "eth_defines.v"
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`include "eth_timescale.v"
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`include "timescale.v"
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module tb_eth_top();
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module tb_eth_top();
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parameter Tp = 1;
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parameter Tp = 1;
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//RX
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//RX
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.mrx_clk_pad_i(MRxClk), .mrxd_pad_i(MRxD), .mrxdv_pad_i(MRxDV), .mrxerr_pad_i(MRxErr),
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.mrx_clk_pad_i(MRxClk), .mrxd_pad_i(MRxD), .mrxdv_pad_i(MRxDV), .mrxerr_pad_i(MRxErr),
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.mcoll_pad_i(MColl), .mcrs_pad_i(MCrs),
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.mcoll_pad_i(MColl), .mcrs_pad_i(MCrs),
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// MIIM
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// MIIM
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.mdc_pad_o(Mdc_O), .md_pad_i(Mdi_I), .md_pad_o(Mdo_O), .md_padoen_o(Mdo_OE)
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.mdc_pad_o(Mdc_O), .md_pad_i(Mdi_I), .md_pad_o(Mdo_O), .md_padoen_o(Mdo_OE),
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.int_o()
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);
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);
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Line 226... |
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initial
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initial
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begin
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begin
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wait(StartTB); // Start of testbench
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wait(StartTB); // Start of testbench
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WishboneWrite(32'h00000800, {`ETH_ETHERNET_SPACE, `ETH_REG_SPACE, 6'h0, `ETH_MODER_ADR<<2}); // r_Rst = 1
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WishboneWrite(32'h00000800, {26'h0, `ETH_MODER_ADR<<2}); // r_Rst = 1
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WishboneWrite(32'h00000000, {`ETH_ETHERNET_SPACE, `ETH_REG_SPACE, 6'h0, `ETH_MODER_ADR<<2}); // r_Rst = 0
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WishboneWrite(32'h00000000, {26'h0, `ETH_MODER_ADR<<2}); // r_Rst = 0
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WishboneWrite(32'h00000080, {`ETH_ETHERNET_SPACE, `ETH_REG_SPACE, 6'h0, `ETH_RX_BD_ADR_ADR<<2});// r_RxBDAddress = 0x80
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WishboneWrite(32'h00000080, {26'h0, `ETH_RX_BD_ADR_ADR<<2}); // r_RxBDAddress = 0x80
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WishboneWrite(32'h0002A443, {`ETH_ETHERNET_SPACE, `ETH_REG_SPACE, 6'h0, `ETH_MODER_ADR<<2}); // RxEn, Txen, FullD, CrcEn, Pad, DmaEn, r_IFG
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WishboneWrite(32'h0002A443, {26'h0, `ETH_MODER_ADR<<2}); // RxEn, Txen, FullD, CrcEn, Pad, DmaEn, r_IFG
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WishboneWrite(32'h00000004, {`ETH_ETHERNET_SPACE, `ETH_REG_SPACE, 6'h0, `ETH_CTRLMODER_ADR<<2});//r_TxFlow = 1
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WishboneWrite(32'h00000004, {26'h0, `ETH_CTRLMODER_ADR<<2}); //r_TxFlow = 1
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SendPacket(16'h0015, 1'b0);
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SendPacket(16'h0015, 1'b0);
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ReceivePacket(16'h0016, 1'b0); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
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ReceivePacket(16'h0016, 1'b0); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
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ReceivePacket(16'h0017, 1'b0); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
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ReceivePacket(16'h0017, 1'b0); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
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ReceivePacket(16'h0018, 1'b0); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
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ReceivePacket(16'h0018, 1'b0); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
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WishboneRead({`ETH_ETHERNET_SPACE, `ETH_REG_SPACE, 6'h0, `ETH_MODER_ADR<<2}); // Read from MODER register
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WishboneRead({26'h0, `ETH_MODER_ADR}); // Read from MODER register
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WishboneRead({`ETH_ETHERNET_SPACE, `ETH_BD_SPACE, 2'h0, (10'h0<<2)}); // Read from TxBD register
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WishboneRead({24'h100, (8'h0<<2)}); // Read from TxBD register
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WishboneRead({`ETH_ETHERNET_SPACE, `ETH_BD_SPACE, 2'h0, (10'h1<<2)}); // Read from TxBD register
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WishboneRead({24'h100, (8'h1<<2)}); // Read from TxBD register
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WishboneRead({`ETH_ETHERNET_SPACE, `ETH_BD_SPACE, 2'h0, (10'h2<<2)}); // Read from TxBD register
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WishboneRead({24'h100, (8'h2<<2)}); // Read from TxBD register
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WishboneRead({`ETH_ETHERNET_SPACE, `ETH_BD_SPACE, 2'h0, (10'h3<<2)}); // Read from TxBD register
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WishboneRead({24'h100, (8'h3<<2)}); // Read from TxBD register
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WishboneRead({`ETH_ETHERNET_SPACE, `ETH_BD_SPACE, 2'h0, (10'h4<<2)}); // Read from TxBD register
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WishboneRead({24'h100, (8'h4<<2)}); // Read from TxBD register
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WishboneRead({`ETH_ETHERNET_SPACE, `ETH_BD_SPACE, 2'h0, (10'h80<<2)}); // Read from RxBD register
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WishboneRead({22'h40, (10'h80<<2)}); // Read from RxBD register
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WishboneRead({`ETH_ETHERNET_SPACE, `ETH_BD_SPACE, 2'h0, (10'h81<<2)}); // Read from RxBD register
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WishboneRead({22'h40, (10'h81<<2)}); // Read from RxBD register
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WishboneRead({`ETH_ETHERNET_SPACE, `ETH_BD_SPACE, 2'h0, (10'h82<<2)}); // Read from RxBD register
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WishboneRead({22'h40, (10'h82<<2)}); // Read from RxBD register
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WishboneRead({`ETH_ETHERNET_SPACE, `ETH_BD_SPACE, 2'h0, (10'h83<<2)}); // Read from RxBD register
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WishboneRead({22'h40, (10'h83<<2)}); // Read from RxBD register
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WishboneRead({`ETH_ETHERNET_SPACE, `ETH_BD_SPACE, 2'h0, (10'h84<<2)}); // Read from RxBD register
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WishboneRead({22'h40, (10'h84<<2)}); // Read from RxBD register
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#10000 $stop;
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#10000 $stop;
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end
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end
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Line 305... |
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wait(WB_ACK_O); // waiting for acknowledge response
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wait(WB_ACK_O); // waiting for acknowledge response
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// Writing information about the access to the screen
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// Writing information about the access to the screen
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@ (posedge WB_CLK_I);
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@ (posedge WB_CLK_I);
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if(Address[31:16] == `ETH_ETHERNET_SPACE)
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if(~Address[17] & ~Address[16])
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if(Address[15:12] == `ETH_REG_SPACE)
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$write("\nWrite to register (Data: 0x%x, Reg. Addr: 0x%0x)", Data, Address);
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$write("\nWrite to register (Data: 0x%x, Reg. Addr: 0x%0x)", Data, Address[9:2]);
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else
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else
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if(Address[15:12] == `ETH_BD_SPACE)
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if(~Address[17] & Address[16])
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if(Address[9:2] < tb_eth_top.ethtop.r_RxBDAddress)
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if(Address[9:2] < tb_eth_top.ethtop.r_RxBDAddress)
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begin
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begin
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$write("\nWrite to TxBD (Data: 0x%x, TxBD Addr: 0x%0x)\n", Data, Address[9:2]);
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$write("\nWrite to TxBD (Data: 0x%x, TxBD Addr: 0x%0x)\n", Data, Address);
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if(Data[13])
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if(Data[13])
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$write("Send Control packet (PAUSE = 0x%0h)\n", Data[31:16]);
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$write("Send Control packet (PAUSE = 0x%0h)\n", Data[31:16]);
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end
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end
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else
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else
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$write("\nWrite to RxBD (Data: 0x%x, RxBD Addr: 0x%0x)", Data, Address[9:2]);
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$write("\nWrite to RxBD (Data: 0x%x, RxBD Addr: 0x%0x)", Data, Address);
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else
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else
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$write("\nWB write Data: 0x%x Addr: 0x%0x", Data, Address);
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$write("\nWB write ?????????????? Data: 0x%x Addr: 0x%0x", Data, Address);
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else
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$write("\nWARNING !!! WB write to non-ethernet space (Data: 0x%x, Addr: 0x%0x)", Data, Address);
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#1;
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#1;
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WB_ADR_I = 32'hx;
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WB_ADR_I = 32'hx;
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WB_DAT_I = 32'hx;
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WB_DAT_I = 32'hx;
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WB_WE_I = 1'bx;
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WB_WE_I = 1'bx;
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WB_CYC_I = 1'b0;
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WB_CYC_I = 1'b0;
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Line 361... |
Address, $time);
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Address, $time);
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#50 $stop;
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#50 $stop;
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end
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end
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@ (posedge WB_CLK_I);
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@ (posedge WB_CLK_I);
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if(Address[31:16] == `ETH_ETHERNET_SPACE)
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if(~Address[17] & ~Address[16])
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if(Address[15:12] == `ETH_REG_SPACE)
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$write("\nRead from register (Data: 0x%x, Reg. Addr: 0x%0x)", Data, Address);
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$write("\nRead from register (Data: 0x%x, Reg. Addr: 0x%0x)", Data, Address[9:2]);
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else
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else
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if(Address[15:12] == `ETH_BD_SPACE)
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if(~Address[17] & Address[16])
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if(Address[9:2] < tb_eth_top.ethtop.r_RxBDAddress)
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if(Address[9:2] < tb_eth_top.ethtop.r_RxBDAddress)
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begin
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begin
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$write("\nRead from TxBD (Data: 0x%x, TxBD Addr: 0x%0x)", Data, Address[9:2]);
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$write("\nRead from TxBD (Data: 0x%x, TxBD Addr: 0x%0x)", Data, Address);
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end
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end
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else
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else
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$write("\nRead from RxBD (Data: 0x%x, RxBD Addr: 0x%0x)", Data, Address[9:2]);
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$write("\nRead from RxBD (Data: 0x%x, RxBD Addr: 0x%0x)", Data, Address);
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else
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$write("\nWB read Data: 0x%x Addr: 0x%0x", Data, Address);
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else
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else
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$write("\nWARNING !!! WB read to non-ethernet space (Data: 0x%x, Addr: 0x%0x)", Data, Address);
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$write("\nWB read ????????? Data: 0x%x Addr: 0x%0x", Data, Address);
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#1;
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#1;
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WB_ADR_I = 32'hx;
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WB_ADR_I = 32'hx;
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WB_WE_I = 1'bx;
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WB_WE_I = 1'bx;
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WB_CYC_I = 1'b0;
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WB_CYC_I = 1'b0;
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WB_STB_I = 1'b0;
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WB_STB_I = 1'b0;
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Line 399... |
if(TxBDIndex == 3) // Only 4 buffer descriptors are used
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if(TxBDIndex == 3) // Only 4 buffer descriptors are used
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Wrap = 1'b1;
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Wrap = 1'b1;
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else
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else
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Wrap = 1'b0;
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Wrap = 1'b0;
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TempAddr = {`ETH_ETHERNET_SPACE, `ETH_BD_SPACE, 2'h0, (TxBDIndex<<2)};
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TempAddr = {22'h40, (TxBDIndex<<2)};
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TempData = {Length[15:0], 1'b1, Wrap, ControlFrame, 5'h0, TxBDIndex[7:0]}; // Ready and Wrap = 1
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TempData = {Length[15:0], 1'b1, 1'b0, Wrap, 3'h0, ControlFrame, 1'b0, TxBDIndex[7:0]}; // Ready and Wrap = 1
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#1;
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#1;
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if(TxBDIndex == 3) // Only 4 buffer descriptors are used
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if(TxBDIndex == 3) // Only 4 buffer descriptors are used
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TxBDIndex = 0;
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TxBDIndex = 0;
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else
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else
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if(RxBDIndex == 3) // Only 4 buffer descriptors are used
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if(RxBDIndex == 3) // Only 4 buffer descriptors are used
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WrapRx = 1'b1;
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WrapRx = 1'b1;
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else
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else
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WrapRx = 1'b0;
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WrapRx = 1'b0;
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TempRxAddr = {`ETH_ETHERNET_SPACE, `ETH_BD_SPACE, 2'h0, ((tb_eth_top.ethtop.r_RxBDAddress + RxBDIndex)<<2)};
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TempRxAddr = {22'h40, ((tb_eth_top.ethtop.r_RxBDAddress + RxBDIndex)<<2)};
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TempRxData = {LengthRx[15:0], 1'b1, WrapRx, 6'h0, RxBDIndex[7:0]}; // Ready and WrapRx = 1 or 0
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TempRxData = {LengthRx[15:0], 1'b1, 1'b0, WrapRx, 5'h0, RxBDIndex[7:0]}; // Ready and WrapRx = 1 or 0
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#1;
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#1;
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if(RxBDIndex == 3) // Only 4 buffer descriptors are used
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if(RxBDIndex == 3) // Only 4 buffer descriptors are used
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RxBDIndex = 0;
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RxBDIndex = 0;
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else
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else
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Line 489... |
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wait (~WishboneBusy);
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wait (~WishboneBusy);
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WishboneBusy = 1;
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WishboneBusy = 1;
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#1;
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#1;
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WB_DAT_I = {a, b, c, d};
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WB_DAT_I = {a, b, c, d};
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WB_ADR_I = {`ETH_ETHERNET_SPACE, `ETH_TX_DATA, pp[11:0]};
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WB_ADR_I = {20'h20, pp[11:0]};
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$display("task WaitingForTxDMARequest: pp=%0d, WB_ADR_I=0x%0h, WB_DAT_I=0x%0h", pp, WB_ADR_I, WB_DAT_I);
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$display("task WaitingForTxDMARequest: pp=%0d, WB_ADR_I=0x%0h, WB_DAT_I=0x%0h", pp, WB_ADR_I, WB_DAT_I);
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WB_WE_I = 1'b1;
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WB_WE_I = 1'b1;
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WB_CYC_I = 1'b1;
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WB_CYC_I = 1'b1;
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WB_STB_I = 1'b1;
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WB_STB_I = 1'b1;
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Line 525... |
repeat(Delay) @(posedge WB_CLK_I);
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repeat(Delay) @(posedge WB_CLK_I);
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wait (~WishboneBusy);
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wait (~WishboneBusy);
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WishboneBusy = 1;
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WishboneBusy = 1;
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#1;
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#1;
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WB_ADR_I = {`ETH_ETHERNET_SPACE, `ETH_RX_DATA, rr[11:0]};
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WB_ADR_I = {20'h20, rr[11:0]};
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$display("task WaitingForRxDMARequest: rr=%0d, WB_ADR_I=0x%0h, WB_DAT_O=0x%0h", rr, WB_ADR_I, WB_DAT_O);
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$display("task WaitingForRxDMARequest: rr=%0d, WB_ADR_I=0x%0h, WB_DAT_O=0x%0h", rr, WB_ADR_I, WB_DAT_O);
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WB_WE_I = 1'b1;
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WB_WE_I = 1'b1;
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WB_CYC_I = 1'b1;
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WB_CYC_I = 1'b1;
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WB_STB_I = 1'b1;
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WB_STB_I = 1'b1;
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