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[/] [ethmac/] [trunk/] [bench/] [verilog/] [tb_eth_top.v] - Diff between revs 49 and 51

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Rev 49 Rev 51
Line 244... Line 244...
  GSR           =  1'b0;
  GSR           =  1'b0;
  #100 StartTB  =  1'b1;
  #100 StartTB  =  1'b1;
end
end
 
 
 
 
assign glbl.GSR = GSR;
//assign glbl.GSR = GSR;
 
 
 
 
 
 
// Generating WB_CLK_I clock
// Generating WB_CLK_I clock
always
always
Line 285... Line 285...
  WishboneWrite(32'h00000800, {26'h0, `ETH_MODER_ADR<<2});     // r_Rst = 1
  WishboneWrite(32'h00000800, {26'h0, `ETH_MODER_ADR<<2});     // r_Rst = 1
  WishboneWrite(32'h00000000, {26'h0, `ETH_MODER_ADR<<2});     // r_Rst = 0
  WishboneWrite(32'h00000000, {26'h0, `ETH_MODER_ADR<<2});     // r_Rst = 0
  WishboneWrite(32'h00000080, {26'h0, `ETH_TX_BD_NUM_ADR<<2}); // r_RxBDAddress = 0x80
  WishboneWrite(32'h00000080, {26'h0, `ETH_TX_BD_NUM_ADR<<2}); // r_RxBDAddress = 0x80
  WishboneWrite(32'h0002A443, {26'h0, `ETH_MODER_ADR<<2});     // RxEn, Txen, FullD, CrcEn, Pad, DmaEn, r_IFG
  WishboneWrite(32'h0002A443, {26'h0, `ETH_MODER_ADR<<2});     // RxEn, Txen, FullD, CrcEn, Pad, DmaEn, r_IFG
  WishboneWrite(32'h00000004, {26'h0, `ETH_CTRLMODER_ADR<<2}); //r_TxFlow = 1
  WishboneWrite(32'h00000004, {26'h0, `ETH_CTRLMODER_ADR<<2}); //r_TxFlow = 1
 
  WishboneWrite(32'h0040000, {26'h0, `ETH_HASH1_ADR,2'h0}); // set bit 16, multicast hash 36
 
 
 
 
 
 
  SendPacket(16'h0015, 1'b0);
  SendPacket(16'h0015, 1'b0);
  SendPacket(16'h0043, 1'b1);   // Control frame
  SendPacket(16'h0043, 1'b1);   // Control frame
Line 699... Line 699...
`else // No WISHBONE_DMA
`else // No WISHBONE_DMA
 
 
initial
initial
begin
begin
  wait(StartTB);  // Start of testbench
  wait(StartTB);  // Start of testbench
 
  //IGORS_BOILER_PLATE;
 
  // TestUnicast;
 
  // TestBroadcast;
 
   TestMulticast;
 
end
 
 
  WishboneWrite(32'h00000800, {26'h0, `ETH_MODER_ADR<<2});     // r_Rst = 1
task IGORS_BOILER_PLATE;
  WishboneWrite(32'h00000000, {26'h0, `ETH_MODER_ADR<<2});     // r_Rst = 0
 begin
  WishboneWrite(32'h00000080, {26'h0, `ETH_TX_BD_NUM_ADR<<2}); // r_RxBDAddress = 0x80
  $display("\nBegin IGORS_BOILER_PLATE \n");
 
  WishboneWrite(32'h00000800, {26'h0, `ETH_MODER_ADR, 2'h0});     // r_Rst = 1
 
  WishboneWrite(32'h00000000, {26'h0, `ETH_MODER_ADR, 2'h0});     // r_Rst = 0
 
  WishboneWrite(32'h00000080, {26'h0, `ETH_TX_BD_NUM_ADR, 2'h0}); // r_RxBDAddress = 0x80
 
 
  WishboneWrite(32'h00022043, {26'h0, `ETH_MODER_ADR<<2});     // RxEn, Txen, CrcEn, Pad, DmaEn, r_IFG
  WishboneWrite(32'h0002A443, {26'h0, `ETH_MODER_ADR, 2'h0});     // RxEn, Txen, FullD, CrcEn, Pad, DmaEn, r_IFG
 
 
  WishboneWrite(32'h00000004, {26'h0, `ETH_CTRLMODER_ADR<<2}); //r_TxFlow = 1
  WishboneWrite(32'h00000004, {26'h0, `ETH_CTRLMODER_ADR, 2'h0}); //r_TxFlow = 1
 
 
  WishboneWrite(32'h12345678, {26'h0, `ETH_HASH0_ADR<<2});
 
  WishboneWrite(32'h98765432, {26'h0, `ETH_HASH1_ADR<<2});
 
  WishboneRead({26'h0, `ETH_HASH0_ADR<<2});   // Read from HASH0 register
 
  WishboneRead({26'h0, `ETH_HASH1_ADR<<2});   // Read from HASH1 register
 
 
 
 
 
  SendPacket(16'h0007, 1'b0);
  SendPacket(16'h0010, 1'b0);
 
  SendPacket(16'h0011, 1'b0);
 
  SendPacket(16'h0012, 1'b0);
 
  SendPacket(16'h0013, 1'b0);
 
  SendPacket(16'h0014, 1'b0);
 
 
 
  SendPacket(16'h0030, 1'b0);
 
  SendPacket(16'h0031, 1'b0);
 
  SendPacket(16'h0032, 1'b0);
 
  SendPacket(16'h0033, 1'b0);
 
  SendPacket(16'h0025, 1'b0);
 
  SendPacket(16'h0045, 1'b0);
 
  SendPacket(16'h0025, 1'b0);
 
  SendPacket(16'h0017, 1'b0);
 
 
 
//  ReceivePacket(16'h0012, 1'b1, 1'b0);    
 
// Initializes RxBD and then Sends a control packet on the MRxD[3:0] signals.
 
 
 
 
 
 
 
  WishboneWrite(32'h00400000, {26'h0, `ETH_HASH1_ADR,2'h0}); // set bit 16, multicast hash 36
 
  WishboneRead({26'h0, `ETH_HASH1_ADR});  // read back
 
 
 
  $display("\n Set Hash Filter to accept this Multicast packet, send packets\n");
 
 
 
  ReceivePacket(16'h0015, 1'b0, 1'b0,`MULTICAST_XFR);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
 
  ReceivePacket(16'h0016, 1'b0, 1'b0,`MULTICAST_XFR);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
 
  ReceivePacket(16'h0017, 1'b0, 1'b0,`MULTICAST_XFR);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
 
  ReceivePacket(16'h0018, 1'b0, 1'b0,`MULTICAST_XFR);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
 
 
 
  repeat(5000) @ (posedge MRxClk);        // Waiting some time for all accesses to finish before reading out the statuses.
 
 
 
  WishboneRead({26'h0, `ETH_MODER_ADR});   // Read from MODER register
 
 
 
  WishboneRead({24'h04, (8'h0<<2)});       // Read from TxBD register
 
  WishboneRead({24'h04, (8'h1<<2)});       // Read from TxBD register
 
  WishboneRead({24'h04, (8'h2<<2)});       // Read from TxBD register
 
  WishboneRead({24'h04, (8'h3<<2)});       // Read from TxBD register
 
  WishboneRead({24'h04, (8'h4<<2)});       // Read from TxBD register
 
 
 
 
 
  WishboneRead({22'h01, (10'h80<<2)});       // Read from RxBD register
 
  WishboneRead({22'h01, (10'h81<<2)});       // Read from RxBD register
 
  WishboneRead({22'h01, (10'h82<<2)});       // Read from RxBD register
 
  WishboneRead({22'h01, (10'h83<<2)});       // Read from RxBD register
 
  WishboneRead({22'h01, (10'h84<<2)});       // Read from RxBD register
 
  WishboneRead({22'h01, (10'h85<<2)});       // Read from RxBD register
 
  WishboneRead({22'h01, (10'h86<<2)});       // Read from RxBD register
 
  WishboneRead({22'h01, (10'h87<<2)});       // Read from RxBD register
 
 
 
  #100000 $stop;
 
  $display("\nEnd IGORS_BOILER_PLATE \n");
 
  end
 
  endtask //IGORS_BOILER_PLATE
 
 
 
task TestUnicast;
 
 begin
 
  $display("\nBegin TestUnicast \n");
 
  WishboneWrite(32'h00000800, {26'h0, `ETH_MODER_ADR, 2'h0});     // r_Rst = 1
 
  WishboneWrite(32'h00000000, {26'h0, `ETH_MODER_ADR, 2'h0});     // r_Rst = 0
 
  WishboneWrite(32'h00000080, {26'h0, `ETH_TX_BD_NUM_ADR, 2'h0}); // r_RxBDAddress = 0x80
 
 
 
  WishboneWrite(32'h0002A443, {26'h0, `ETH_MODER_ADR, 2'h0});     // RxEn, Txen, FullD, CrcEn, Pad, DmaEn, r_IFG
 
 
 
  WishboneWrite(32'h00000004, {26'h0, `ETH_CTRLMODER_ADR, 2'h0}); //r_TxFlow = 1
 
 
 
 
 
 
 
  SendPacket(16'h0010, 1'b0);
  SendPacket(16'h0011, 1'b0);
  SendPacket(16'h0011, 1'b0);
  SendPacket(16'h0012, 1'b0);
  SendPacket(16'h0012, 1'b0);
  SendPacket(16'h0013, 1'b0);
  SendPacket(16'h0013, 1'b0);
  SendPacket(16'h0014, 1'b0);
  SendPacket(16'h0014, 1'b0);
 
 
Line 730... Line 802...
  SendPacket(16'h0045, 1'b0);
  SendPacket(16'h0045, 1'b0);
  SendPacket(16'h0025, 1'b0);
  SendPacket(16'h0025, 1'b0);
  SendPacket(16'h0017, 1'b0);
  SendPacket(16'h0017, 1'b0);
 
 
//  ReceivePacket(16'h0012, 1'b1, 1'b0);    // Initializes RxBD and then Sends a control packet on the MRxD[3:0] signals.
//  ReceivePacket(16'h0012, 1'b1, 1'b0);    // Initializes RxBD and then Sends a control packet on the MRxD[3:0] signals.
  ReceivePacket(16'h000b, 1'b0, 1'b0);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
 $display("\n This Uniicast packet will be rejected, wrong address in MAC Address Regs\n");
  ReceivePacket(16'h0016, 1'b0, 1'b0);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
 
  ReceivePacket(16'h0017, 1'b0, 1'b0);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
  ReceivePacket(16'h0015, 1'b0, 1'b0,`UNICAST_XFR);
  ReceivePacket(16'h0018, 1'b0, 1'b0);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
 
 
  WishboneWrite(32'h04030200, {26'h0,`ETH_MAC_ADDR0_ADR ,2'h0}); // Mac Address 
 
  WishboneWrite(32'h00000605, {26'h0,`ETH_MAC_ADDR1_ADR ,2'h0}); // Mac Address
 
 
 
 
 
  $display("\n Set Proper Unicast Address in MAC_ADDRESS regs, resend packet\n");
 
 
 
  ReceivePacket(16'h0015, 1'b0, 1'b0,`UNICAST_XFR);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
 
  ReceivePacket(16'h0016, 1'b0, 1'b0,`UNICAST_XFR);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
 
  ReceivePacket(16'h0017, 1'b0, 1'b0,`UNICAST_XFR);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
 
  ReceivePacket(16'h0018, 1'b0, 1'b0,`UNICAST_XFR);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
 
 
  repeat(5000) @ (posedge MRxClk);        // Waiting some time for all accesses to finish before reading out the statuses.
  repeat(5000) @ (posedge MRxClk);        // Waiting some time for all accesses to finish before reading out the statuses.
 
 
  WishboneRead({26'h0, `ETH_MODER_ADR});   // Read from MODER register
  WishboneRead({26'h0, `ETH_MODER_ADR});   // Read from MODER register
 
 
Line 756... Line 838...
  WishboneRead({22'h01, (10'h85<<2)});       // Read from RxBD register
  WishboneRead({22'h01, (10'h85<<2)});       // Read from RxBD register
  WishboneRead({22'h01, (10'h86<<2)});       // Read from RxBD register
  WishboneRead({22'h01, (10'h86<<2)});       // Read from RxBD register
  WishboneRead({22'h01, (10'h87<<2)});       // Read from RxBD register
  WishboneRead({22'h01, (10'h87<<2)});       // Read from RxBD register
 
 
  #100000 $stop;
  #100000 $stop;
 
  $display("\nEnd TestUnicast \n");
end
end
 
endtask //TestUnicast
 
 
integer ijk;
task TestMulticast;
 
 begin
 
  $display("\nBegin TestMulticast \n");
 
  WishboneWrite(32'h00000800, {26'h0, `ETH_MODER_ADR, 2'h0});     // r_Rst = 1
 
  WishboneWrite(32'h00000000, {26'h0, `ETH_MODER_ADR, 2'h0});     // r_Rst = 0
 
  WishboneWrite(32'h00000080, {26'h0, `ETH_TX_BD_NUM_ADR, 2'h0}); // r_RxBDAddress = 0x80
 
 
initial
  WishboneWrite(32'h0002A443, {26'h0, `ETH_MODER_ADR, 2'h0});     // RxEn, Txen, FullD, CrcEn, Pad, DmaEn, r_IFG
ijk = 0;    // for stoping generation of the m_wb_ack_i signal at the right moment so we get underrun
 
 
 
// Answering to master Wishbone requests
  WishboneWrite(32'h00000004, {26'h0, `ETH_CTRLMODER_ADR, 2'h0}); //r_TxFlow = 1
//wire [31:0] daatax = 32'h87654321;
 
//wire [31:0] daatay = 32'h00edcba9;
 
 
 
 
  SendPacket(16'h0010, 1'b0);
 
  SendPacket(16'h0011, 1'b0);
 
  SendPacket(16'h0012, 1'b0);
 
  SendPacket(16'h0013, 1'b0);
 
  SendPacket(16'h0014, 1'b0);
 
 
 
  SendPacket(16'h0030, 1'b0);
 
  SendPacket(16'h0031, 1'b0);
 
  SendPacket(16'h0032, 1'b0);
 
  SendPacket(16'h0033, 1'b0);
 
  SendPacket(16'h0025, 1'b0);
 
  SendPacket(16'h0045, 1'b0);
 
  SendPacket(16'h0025, 1'b0);
 
  SendPacket(16'h0017, 1'b0);
 
 
 
//  ReceivePacket(16'h0012, 1'b1, 1'b0);    
 
// Initializes RxBD and then Sends a control packet on the MRxD[3:0] signals.
 
 
 
 $display("\n This Multicast packet will be rejected by Hash Filter\n");
 
 
 
  ReceivePacket(16'h0015, 1'b0, 1'b0,`MULTICAST_XFR);
 
 
 
  WishboneWrite(32'h00400000, {26'h0, `ETH_HASH1_ADR,2'h0}); // set bit 16, multicast hash 36
 
  WishboneRead({26'h0, `ETH_HASH1_ADR});  // read back
 
 
 
  $display("\n Set Hash Filter to accept this Multicast packet, resend packet\n");
 
 
 
  ReceivePacket(16'h0015, 1'b0, 1'b0,`MULTICAST_XFR);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
 
  ReceivePacket(16'h0016, 1'b0, 1'b0,`MULTICAST_XFR);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
 
  ReceivePacket(16'h0017, 1'b0, 1'b0,`MULTICAST_XFR);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
 
  ReceivePacket(16'h0018, 1'b0, 1'b0,`MULTICAST_XFR);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
 
 
 
  repeat(5000) @ (posedge MRxClk);        // Waiting some time for all accesses to finish before reading out the statuses.
 
 
 
  WishboneRead({26'h0, `ETH_MODER_ADR});   // Read from MODER register
 
 
 
  WishboneRead({24'h04, (8'h0<<2)});       // Read from TxBD register
 
  WishboneRead({24'h04, (8'h1<<2)});       // Read from TxBD register
 
  WishboneRead({24'h04, (8'h2<<2)});       // Read from TxBD register
 
  WishboneRead({24'h04, (8'h3<<2)});       // Read from TxBD register
 
  WishboneRead({24'h04, (8'h4<<2)});       // Read from TxBD register
 
 
 
 
 
  WishboneRead({22'h01, (10'h80<<2)});       // Read from RxBD register
 
  WishboneRead({22'h01, (10'h81<<2)});       // Read from RxBD register
 
  WishboneRead({22'h01, (10'h82<<2)});       // Read from RxBD register
 
  WishboneRead({22'h01, (10'h83<<2)});       // Read from RxBD register
 
  WishboneRead({22'h01, (10'h84<<2)});       // Read from RxBD register
 
  WishboneRead({22'h01, (10'h85<<2)});       // Read from RxBD register
 
  WishboneRead({22'h01, (10'h86<<2)});       // Read from RxBD register
 
  WishboneRead({22'h01, (10'h87<<2)});       // Read from RxBD register
 
 
 
  #100000 $stop;
 
  $display("\nEnd TestMulticast \n");
 
end
 
endtask //TestMulticast
 
 
 
 
 
task TestBroadcast;
 
 begin
 
  $display("\nBegin TestBroadcast \n");
 
  WishboneWrite(32'h00000800, {26'h0, `ETH_MODER_ADR, 2'h0});     // r_Rst = 1
 
  WishboneWrite(32'h00000000, {26'h0, `ETH_MODER_ADR, 2'h0});     // r_Rst = 0
 
  WishboneWrite(32'h00000080, {26'h0, `ETH_TX_BD_NUM_ADR, 2'h0}); // r_RxBDAddress = 0x80
 
 
 
  WishboneWrite(32'h0002A44b, {26'h0, `ETH_MODER_ADR, 2'h0});
 
  // RxEn, Txen, FullD, CrcEn, Pad, DmaEn, r_IFG, r_Bro = 1 (disabled)
 
 
 
  WishboneWrite(32'h00000004, {26'h0, `ETH_CTRLMODER_ADR, 2'h0}); //r_TxFlow = 1
 
 
 
 
 
 
 
  SendPacket(16'h0010, 1'b0);
 
  SendPacket(16'h0011, 1'b0);
 
  SendPacket(16'h0012, 1'b0);
 
  SendPacket(16'h0013, 1'b0);
 
  SendPacket(16'h0014, 1'b0);
 
 
 
  SendPacket(16'h0030, 1'b0);
 
  SendPacket(16'h0031, 1'b0);
 
  SendPacket(16'h0032, 1'b0);
 
  SendPacket(16'h0033, 1'b0);
 
  SendPacket(16'h0025, 1'b0);
 
  SendPacket(16'h0045, 1'b0);
 
  SendPacket(16'h0025, 1'b0);
 
  SendPacket(16'h0017, 1'b0);
 
 
 
//  ReceivePacket(16'h0012, 1'b1, 1'b0);    
 
// Initializes RxBD and then Sends a control packet on the MRxD[3:0] signals.
 
 
 
 $display("\n This Broadcast packet will be rejected ,r_BRO  set\n");
 
 
 
  ReceivePacket(16'h0015, 1'b0, 1'b0,`BROADCAST_XFR);
 
 
 
 
 
  WishboneWrite(32'h0002A443, {26'h0, `ETH_MODER_ADR, 2'h0});
 
 
 
  // RxEn, Txen, FullD, CrcEn, Pad, DmaEn, r_IFG, r_Bro
 
  $display("\n Set r_Bro, resend packet\n");
 
 
 
  ReceivePacket(16'h0015, 1'b0, 1'b0,`BROADCAST_XFR);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
 
  ReceivePacket(16'h0016, 1'b0, 1'b0,`BROADCAST_XFR);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
 
  ReceivePacket(16'h0017, 1'b0, 1'b0,`BROADCAST_XFR);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
 
  ReceivePacket(16'h0018, 1'b0, 1'b0,`BROADCAST_XFR);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
 
 
 
  repeat(5000) @ (posedge MRxClk);        // Waiting some time for all accesses to finish before reading out the statuses.
 
 
 
  WishboneRead({26'h0, `ETH_MODER_ADR});   // Read from MODER register
 
 
 
  WishboneRead({24'h04, (8'h0<<2)});       // Read from TxBD register
 
  WishboneRead({24'h04, (8'h1<<2)});       // Read from TxBD register
 
  WishboneRead({24'h04, (8'h2<<2)});       // Read from TxBD register
 
  WishboneRead({24'h04, (8'h3<<2)});       // Read from TxBD register
 
  WishboneRead({24'h04, (8'h4<<2)});       // Read from TxBD register
 
 
 
 
 
  WishboneRead({22'h01, (10'h80<<2)});       // Read from RxBD register
 
  WishboneRead({22'h01, (10'h81<<2)});       // Read from RxBD register
 
  WishboneRead({22'h01, (10'h82<<2)});       // Read from RxBD register
 
  WishboneRead({22'h01, (10'h83<<2)});       // Read from RxBD register
 
  WishboneRead({22'h01, (10'h84<<2)});       // Read from RxBD register
 
  WishboneRead({22'h01, (10'h85<<2)});       // Read from RxBD register
 
  WishboneRead({22'h01, (10'h86<<2)});       // Read from RxBD register
 
  WishboneRead({22'h01, (10'h87<<2)});       // Read from RxBD register
 
 
 
  #100000 $stop;
 
  $display("\nEnd TestBroadcast \n");
 
end
 
endtask //TestBroadcast
 
 
 
//integer ijk;
 
 
 
//initial
 
//ijk = 0;    // for stoping generation of the m_wb_ack_i signal at the right moment so we get underrun
 
 
 
// Answering to master Wishbone requests
always @ (posedge WB_CLK_I)
always @ (posedge WB_CLK_I)
begin
begin
  if(m_wb_cyc_o & m_wb_stb_o) // Add valid address range
  if(m_wb_cyc_o & m_wb_stb_o) // Add valid address range
    begin
    begin
      repeat(3) @ (posedge WB_CLK_I);
      repeat(3) @ (posedge WB_CLK_I);
        begin
        begin
          if(ijk==6) // mama
//          if(ijk==41)
            MColl = 1;
 
//          if(ijk==9)
 
          else
 
            MColl = 0;
 
//            begin
//            begin
//              repeat(1000) @ (posedge WB_CLK_I);
//              repeat(1000) @ (posedge WB_CLK_I);
//            end
//            end
//          else
//          else
            m_wb_ack_i <=#Tp 1'b1;
            m_wb_ack_i <=#Tp 1'b1;
          if(~m_wb_we_o)
          if(~m_wb_we_o)
            begin
            begin
              #Tp m_wb_dat_i = m_wb_adr_o + 1'b1; // For easier following of the data
              #Tp m_wb_dat_i = m_wb_adr_o + 1'b1; // For easier following of the data
//                #Tp m_wb_dat_i = ijk? daatay : daatax;
 
              $fdisplay(mcd1, "(%0t) master read (0x%0x) = 0x%0x", $time, m_wb_adr_o, m_wb_dat_i);
              $fdisplay(mcd1, "(%0t) master read (0x%0x) = 0x%0x", $time, m_wb_adr_o, m_wb_dat_i);
 
//              ijk = ijk + 1;
            end
            end
          else
          else
            $fdisplay(mcd2, "(%0t) master write (0x%0x) = 0x%0x", $time, m_wb_adr_o, m_wb_dat_o);
            $fdisplay(mcd2, "(%0t) master write (0x%0x) = 0x%0x", $time, m_wb_adr_o, m_wb_dat_o);
        end
        end
      @ (posedge WB_CLK_I);
      @ (posedge WB_CLK_I);
      ijk = ijk + 1;
 
      m_wb_ack_i <=#Tp 1'b0;
      m_wb_ack_i <=#Tp 1'b0;
    end
    end
end
end
 
 
// Generating error
// Generating error
Line 918... Line 1137...
    TempAddr = {22'h01, ((TxBDIndex + 1'b1)<<2)};
    TempAddr = {22'h01, ((TxBDIndex + 1'b1)<<2)};
    TempData = 32'h78563411;
    TempData = 32'h78563411;
    WishboneWrite(TempData, TempAddr); // buffer pointer
    WishboneWrite(TempData, TempAddr); // buffer pointer
 
 
 
 
    TempAddr = {22'h01, (TxBDIndex<<2)};
    TempAddr = {22'h01, (TxBDIndex<<2)};  // igor !!! zbrisi spodnjo vrstico
 
//    TempAddr = {22'h01, 10'b1010010100};
 
 
    TempData = {Length[15:0], 1'b1, 1'b0, Wrap, 3'h0, ControlFrame, 1'b0, TxBDIndex[7:0]};  // Ready and Wrap = 1
    TempData = {Length[15:0], 1'b1, 1'b0, Wrap, 3'h0, ControlFrame, 1'b0, TxBDIndex[7:0]};  // Ready and Wrap = 1
 
 
    #1;
    #1;
//    if(TxBDIndex == 6)    // Only 4 buffer descriptors are used
//    if(TxBDIndex == 6)    // Only 4 buffer descriptors are used
Line 938... Line 1158...
 
 
task ReceivePacket;    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
task ReceivePacket;    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
  input [15:0] LengthRx;
  input [15:0] LengthRx;
  input        RxControlFrame;
  input        RxControlFrame;
  input        Abort;
  input        Abort;
 
  input [31:0] TransferType;  //Broadcast,Unicast,Multicast
  reg        WrapRx;
  reg        WrapRx;
  reg [31:0] TempRxAddr;
  reg [31:0] TempRxAddr;
  reg [31:0] TempRxData;
  reg [31:0] TempRxData;
  reg abc;
  reg abc;
  begin
  begin
Line 972... Line 1193...
      begin
      begin
        #200;
        #200;
        if(RxControlFrame)
        if(RxControlFrame)
          GetControlDataOnMRxD(LengthRx); // LengthRx = PAUSE timer value.
          GetControlDataOnMRxD(LengthRx); // LengthRx = PAUSE timer value.
        else
        else
          GetDataOnMRxD(LengthRx, Abort); // LengthRx bytes is comming on MRxD[3:0] signals
          GetDataOnMRxD(LengthRx, Abort, TransferType); // LengthRx bytes is comming on MRxD[3:0] signals
      end
      end
 
 
  end
  end
endtask
endtask
 
 
 
 
task GetDataOnMRxD;
task GetDataOnMRxD;
  input [15:0] Len;
  input [15:0] Len;
  input abort;
  input abort;
 
  input [31:0] TransferType;
  integer tt;
  integer tt;
 
 
//  reg [87:0] ddata;
 
 
 
  begin
  begin
//    ddata = 88'h50727196edcba987654321;
 
 
 
    @ (posedge MRxClk);
    @ (posedge MRxClk);
    MRxDV=1'b1;
    MRxDV=1'b1;
 
 
    for(tt=0; tt<15; tt=tt+1)
    for(tt=0; tt<15; tt=tt+1)
    begin
    begin
Line 1000... Line 1218...
      @ (posedge MRxClk);
      @ (posedge MRxClk);
    end
    end
    MRxD=4'hd;                // SFD
    MRxD=4'hd;                // SFD
 
 
    for(tt=1; tt<(Len+1); tt=tt+1)
    for(tt=1; tt<(Len+1); tt=tt+1)
 
 
    begin
    begin
 
 
      @ (posedge MRxClk);
      @ (posedge MRxClk);
      MRxD=tt[3:0];
          if(TransferType == `UNICAST_XFR && tt == 1)
 
           MRxD= 4'h0;   // Unicast transfer
 
          else if(TransferType == `BROADCAST_XFR && tt < 7)
 
           MRxD = 4'hf;
 
          else
 
       MRxD=tt[3:0]; // Multicast transfer
 
 
      if(tt==9)
      if(tt==9)
        RxAbort<=#1 abort;
        RxAbort<=#1 abort;
      @ (posedge MRxClk);
      @ (posedge MRxClk);
 
 
 
           if(TransferType == `BROADCAST_XFR && tt < 7)
 
            MRxD = 4'hf;
 
          else
      MRxD=tt[7:4];
      MRxD=tt[7:4];
      RxAbort<=#1 0;
      RxAbort<=#1 0;
    end
    end
/*
 
    for(tt=0; tt<Len; tt=tt+1)
 
    begin
 
      @ (posedge MRxClk);
 
      MRxD=ddata[3:0];
 
      $display("MRxD=0x%0x", MRxD);
 
      if(tt==9)
 
        RxAbort<=#1 abort;
 
      @ (posedge MRxClk);
 
      MRxD=ddata[7:4];
 
      $display("MRxD=0x%0x", MRxD);
 
      ddata[87:0] = {8'h0, ddata[87:8]};
 
 
 
      RxAbort<=#1 0;
 
    end
 
*/
 
    @ (posedge MRxClk);
    @ (posedge MRxClk);
    MRxDV=1'b0;
    MRxDV=1'b0;
  end
  end
endtask
endtask
 
 
Line 1039... Line 1254...
  reg [127:0] Data;
  reg [127:0] Data;
  reg [31:0] Crc;
  reg [31:0] Crc;
  integer tt;
  integer tt;
 
 
  begin
  begin
  Packet = 128'h10082C000010_deadbeef0013_8880_0010; // 0180c2000001 + 8808 + 0001
   //Packet = 128'h10082C000010_deadbeef0013_8880_0010; // 0180c2000001 + 8808 + 0001
 
 
  Crc = 32'h6014fe08; // not a correct value
  Crc = 32'h6014fe08; // not a correct value
 
 
    @ (posedge MRxClk);
    @ (posedge MRxClk);
    MRxDV=1'b1;
    MRxDV=1'b1;
 
 

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