| Line 39... |
Line 39... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.10 2002/02/16 07:22:15 mohor
|
|
// Testbench fixed, code simplified, unused signals removed.
|
|
//
|
// Revision 1.9 2002/02/14 20:14:38 billditt
|
// Revision 1.9 2002/02/14 20:14:38 billditt
|
// Added separate tests for Multicast, Unicast, Broadcast
|
// Added separate tests for Multicast, Unicast, Broadcast
|
//
|
//
|
// Revision 1.8 2002/02/12 20:24:00 mohor
|
// Revision 1.8 2002/02/12 20:24:00 mohor
|
// HASH0 and HASH1 register read/write added.
|
// HASH0 and HASH1 register read/write added.
|
| Line 111... |
Line 114... |
wire [31:0] WB_DAT_O;
|
wire [31:0] WB_DAT_O;
|
wire WB_ACK_O;
|
wire WB_ACK_O;
|
wire WB_ERR_O;
|
wire WB_ERR_O;
|
reg [1:0] WB_ACK_I;
|
reg [1:0] WB_ACK_I;
|
|
|
`ifdef WISHBONE_DMA
|
`ifdef EXTERNAL_DMA
|
wire [1:0] WB_REQ_O;
|
wire [1:0] WB_REQ_O;
|
wire [1:0] WB_ND_O;
|
wire [1:0] WB_ND_O;
|
wire WB_RD_O;
|
wire WB_RD_O;
|
`else
|
`else
|
// WISHBONE master
|
// WISHBONE master
|
| Line 152... |
Line 155... |
reg WishboneBusy;
|
reg WishboneBusy;
|
reg StartTB;
|
reg StartTB;
|
reg [9:0] TxBDIndex;
|
reg [9:0] TxBDIndex;
|
reg [9:0] RxBDIndex;
|
reg [9:0] RxBDIndex;
|
|
|
`ifdef WISHBONE_DMA
|
`ifdef EXTERNAL_DMA
|
`else
|
`else
|
integer mcd1;
|
integer mcd1;
|
integer mcd2;
|
integer mcd2;
|
`endif
|
`endif
|
|
|
| Line 169... |
Line 172... |
|
|
// WISHBONE slave
|
// WISHBONE slave
|
.wb_adr_i(WB_ADR_I[11:2]), .wb_sel_i(WB_SEL_I), .wb_we_i(WB_WE_I), .wb_cyc_i(WB_CYC_I),
|
.wb_adr_i(WB_ADR_I[11:2]), .wb_sel_i(WB_SEL_I), .wb_we_i(WB_WE_I), .wb_cyc_i(WB_CYC_I),
|
.wb_stb_i(WB_STB_I), .wb_ack_o(WB_ACK_O), .wb_err_o(WB_ERR_O), .wb_ack_i(WB_ACK_I),
|
.wb_stb_i(WB_STB_I), .wb_ack_o(WB_ACK_O), .wb_err_o(WB_ERR_O), .wb_ack_i(WB_ACK_I),
|
|
|
`ifdef WISHBONE_DMA
|
`ifdef EXTERNAL_DMA
|
.wb_req_o(WB_REQ_O), .wb_nd_o(WB_ND_O), .wb_rd_o(WB_RD_O),
|
.wb_req_o(WB_REQ_O), .wb_nd_o(WB_ND_O), .wb_rd_o(WB_RD_O),
|
`else
|
`else
|
// WISHBONE master
|
// WISHBONE master
|
.m_wb_adr_o(m_wb_adr_o), .m_wb_sel_o(m_wb_sel_o), .m_wb_we_o(m_wb_we_o), .m_wb_dat_i(m_wb_dat_i),
|
.m_wb_adr_o(m_wb_adr_o), .m_wb_sel_o(m_wb_sel_o), .m_wb_we_o(m_wb_we_o), .m_wb_dat_i(m_wb_dat_i),
|
.m_wb_dat_o(m_wb_dat_o), .m_wb_cyc_o(m_wb_cyc_o), .m_wb_stb_o(m_wb_stb_o), .m_wb_ack_i(m_wb_ack_i),
|
.m_wb_dat_o(m_wb_dat_o), .m_wb_cyc_o(m_wb_cyc_o), .m_wb_stb_o(m_wb_stb_o), .m_wb_ack_i(m_wb_ack_i),
|
| Line 207... |
Line 210... |
WB_SEL_I = 4'h0;
|
WB_SEL_I = 4'h0;
|
WB_WE_I = 1'b0;
|
WB_WE_I = 1'b0;
|
WB_CYC_I = 1'b0;
|
WB_CYC_I = 1'b0;
|
WB_STB_I = 1'b0;
|
WB_STB_I = 1'b0;
|
|
|
`ifdef WISHBONE_DMA
|
`ifdef EXTERNAL_DMA
|
WB_ACK_I = 2'h0;
|
WB_ACK_I = 2'h0;
|
`else
|
`else
|
m_wb_ack_i = 0;
|
m_wb_ack_i = 0;
|
m_wb_err_i = 0;
|
m_wb_err_i = 0;
|
`endif
|
`endif
|
| Line 231... |
Line 234... |
|
|
|
|
// Reset pulse
|
// Reset pulse
|
initial
|
initial
|
begin
|
begin
|
`ifdef WISHBONE_DMA
|
`ifdef EXTERNAL_DMA
|
`else
|
`else
|
mcd1 = $fopen("ethernet_tx.log");
|
mcd1 = $fopen("ethernet_tx.log");
|
mcd2 = $fopen("ethernet_rx.log");
|
mcd2 = $fopen("ethernet_rx.log");
|
`endif
|
`endif
|
WB_RST_I = 1'b1;
|
WB_RST_I = 1'b1;
|
| Line 270... |
Line 273... |
begin
|
begin
|
#16 forever #20 MRxClk = ~MRxClk; // 2*20 ns -> 25 MHz
|
#16 forever #20 MRxClk = ~MRxClk; // 2*20 ns -> 25 MHz
|
// #16 forever #250 MRxClk = ~MRxClk;
|
// #16 forever #250 MRxClk = ~MRxClk;
|
end
|
end
|
|
|
`ifdef WISHBONE_DMA
|
`ifdef EXTERNAL_DMA
|
initial
|
initial
|
begin
|
begin
|
wait(StartTB); // Start of testbench
|
wait(StartTB); // Start of testbench
|
|
|
WishboneWrite(32'h00000800, {26'h0, `ETH_MODER_ADR<<2}); // r_Rst = 1
|
WishboneWrite(32'h00000800, {26'h0, `ETH_MODER_ADR<<2}); // r_Rst = 1
|
| Line 671... |
Line 674... |
@ (posedge MRxClk);
|
@ (posedge MRxClk);
|
MRxDV=1'b0;
|
MRxDV=1'b0;
|
end
|
end
|
endtask
|
endtask
|
|
|
`else // No WISHBONE_DMA
|
`else // No EXTERNAL_DMA
|
|
|
initial
|
initial
|
begin
|
begin
|
wait(StartTB); // Start of testbench
|
wait(StartTB); // Start of testbench
|
|
|
