| Line 40... |
Line 40... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.16 2002/10/09 13:16:51 tadejm
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|
// Just back-up; not completed testbench and some testcases are not
|
|
// wotking properly yet.
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//
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// Revision 1.15 2002/09/20 14:29:12 tadej
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// Revision 1.15 2002/09/20 14:29:12 tadej
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// Full duplex tests modified and testbench bug repaired.
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// Full duplex tests modified and testbench bug repaired.
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//
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//
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// Revision 1.14 2002/09/18 17:56:38 tadej
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// Revision 1.14 2002/09/18 17:56:38 tadej
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// Some additional reports added
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// Some additional reports added
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| Line 412... |
Line 416... |
// ----------
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// ----------
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// test_access_to_mac_reg(0, 3); // 0 - 3
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// test_access_to_mac_reg(0, 3); // 0 - 3
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// test_mii(0, 17); // 0 - 17
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// test_mii(0, 17); // 0 - 17
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test_note("PHY generates ideal Carrier sense and Collision signals for following tests");
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test_note("PHY generates ideal Carrier sense and Collision signals for following tests");
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eth_phy.carrier_sense_real_delay(0);
|
eth_phy.carrier_sense_real_delay(0);
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test_mac_full_duplex_transmit(0, 21); // 0 - (21)
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test_mac_full_duplex_transmit(20, 20); // 0 - (21)
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test_mac_full_duplex_receive(0, 5);
|
// test_mac_full_duplex_receive(0, 5);
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// test_mac_full_duplex_flow(0, 0);
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// test_mac_full_duplex_flow(0, 0);
|
|
|
test_note("PHY generates 'real' Carrier sense and Collision signals for following tests");
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test_note("PHY generates 'real' Carrier sense and Collision signals for following tests");
|
eth_phy.carrier_sense_real_delay(1);
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eth_phy.carrier_sense_real_delay(1);
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|
|
| Line 9731... |
Line 9735... |
// write to phy's control register for 10Mbps
|
// write to phy's control register for 10Mbps
|
#Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
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#Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
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#Tp eth_phy.control_bit8_0 = 9'h1_00; // bit 6 reset - (10/100), bit 8 set - FD
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#Tp eth_phy.control_bit8_0 = 9'h1_00; // bit 6 reset - (10/100), bit 8 set - FD
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speed = 10;
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speed = 10;
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|
|
num_of_frames = 0; // (0..3) => start under-run on first word
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num_of_frames = 40; // (0..3) => start under-run on first word
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num_of_bd = 0;
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num_of_bd = 0;
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i_data = 3; // (3) => one BYTE read in first word - FIRST byte
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i_data = 3; // (3) => one BYTE read in first word - FIRST byte
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i_length = (min_tmp + 4);
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i_length = (min_tmp + 4);
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while (i_length < (max_tmp - 4))
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while (i_length < (max_tmp - 4))
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begin
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begin
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| Line 9754... |
Line 9758... |
set_tx_bd(0, 0, i_length, 1'b1, 1'b1, 1'b1, (`MEMORY_BASE + i_data[1:0]));
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set_tx_bd(0, 0, i_length, 1'b1, 1'b1, 1'b1, (`MEMORY_BASE + i_data[1:0]));
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set_tx_bd(1, 1, i_length, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
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set_tx_bd(1, 1, i_length, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
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set_tx_bd_wrap(1);
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set_tx_bd_wrap(1);
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// set wb slave response: ACK (response), wbs_waits[2:0] (waits before response),
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// set wb slave response: ACK (response), wbs_waits[2:0] (waits before response),
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// wbs_retries[7:0] (RTYs before ACK if RTY response selected)
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// wbs_retries[7:0] (RTYs before ACK if RTY response selected)
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#1 wb_slave.cycle_response(`ACK_RESPONSE, 3'h2, 8'h0);
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#1 wb_slave.cycle_response(`ACK_RESPONSE, 3'h0, 8'h0);
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set_tx_bd_ready(1, 1);
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set_tx_bd_ready(1, 1);
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set_tx_bd_ready(0, 0);
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set_tx_bd_ready(0, 0);
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end
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end
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// frame under-run checking
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// frame under-run checking
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frame_started = 0;
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frame_started = 0;
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| Line 9770... |
Line 9774... |
// in other words 4 bytes are read, since length is MINFL => num_of_frames[31:2] ACKs
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// in other words 4 bytes are read, since length is MINFL => num_of_frames[31:2] ACKs
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repeat ((num_of_frames[31:2] + 1'b1)) @(posedge eth_ma_wb_ack_i);
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repeat ((num_of_frames[31:2] + 1'b1)) @(posedge eth_ma_wb_ack_i);
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@(negedge eth_ma_wb_ack_i); // wait for last ACK to finish
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@(negedge eth_ma_wb_ack_i); // wait for last ACK to finish
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// set wb slave response: ACK (response), wbs_waits[2:0] (waits before response),
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// set wb slave response: ACK (response), wbs_waits[2:0] (waits before response),
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// wbs_retries[7:0] (RTYs before ACK if RTY response selected)
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// wbs_retries[7:0] (RTYs before ACK if RTY response selected)
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#1 wb_slave.cycle_response(`NO_RESPONSE, 3'h7, 8'hFF);
|
#1 wb_slave.cycle_response(`NO_RESPONSE, 3'h0, 8'hFF);
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// wait for synchronization and some additional clocks
|
// wait for synchronization and some additional clocks
|
wait_for_frame = 1;
|
wait_for_frame = 1;
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// wait for frame
|
// wait for frame
|
wait ((wait_for_frame == 0) || (frame_started == 1))
|
wait ((wait_for_frame == 0) || (frame_started == 1))
|
if ((wait_for_frame == 0) && (frame_started == 0)) // frame didn't start
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if ((wait_for_frame == 0) && (frame_started == 0)) // frame didn't start
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| Line 9787... |
Line 9791... |
wait (frame_ended == 1);
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wait (frame_ended == 1);
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end
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end
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repeat (2) @(posedge wb_clk);
|
repeat (2) @(posedge wb_clk);
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// set wb slave response: ACK (response), wbs_waits[2:0] (waits before response),
|
// set wb slave response: ACK (response), wbs_waits[2:0] (waits before response),
|
// wbs_retries[7:0] (RTYs before ACK if RTY response selected)
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// wbs_retries[7:0] (RTYs before ACK if RTY response selected)
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wb_slave.cycle_response(`ACK_RESPONSE, 3'h2, 8'h0);
|
wb_slave.cycle_response(`ACK_RESPONSE, 3'h0, 8'h0);
|
end
|
end
|
begin: wait_fr
|
begin: wait_fr
|
wait (wait_for_frame == 1)
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wait (wait_for_frame == 1)
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begin
|
begin
|
// wait for synchronization and some additional clocks
|
// wait for synchronization and some additional clocks
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| Line 9804... |
Line 9808... |
end
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end
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begin: check_fr
|
begin: check_fr
|
// wait for frame to start
|
// wait for frame to start
|
@(posedge MTxEn);
|
@(posedge MTxEn);
|
frame_started = 1;
|
frame_started = 1;
|
$display(" Under-run (on %0d. byte) frame started", (num_of_frames + 1));
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`TIME; $display(" Under-run (on %0d. byte) frame started", (num_of_frames + 1));
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// wait for frame to end due to under-run
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// wait for frame to end due to under-run
|
@(negedge MTxEn);
|
@(negedge MTxEn);
|
frame_ended = 1;
|
frame_ended = 1;
|
$display(" Under-run frame ended");
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`TIME; $display(" Under-run frame ended");
|
end
|
end
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join
|
join
|
// wait for first transmit to end, if under-run didn't happen
|
// wait for first transmit to end, if under-run didn't happen
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if (frame_ended == 0)
|
if (frame_ended == 0)
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begin
|
begin
|
| Line 9835... |
Line 9839... |
// check length of a first PACKET
|
// check length of a first PACKET
|
tmp_len = eth_phy.tx_len;
|
tmp_len = eth_phy.tx_len;
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#1;
|
#1;
|
if (tmp_len != (i_length + 4))
|
if (tmp_len != (i_length + 4))
|
begin
|
begin
|
test_fail("Wrong length of second packet out from MAC");
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`TIME; $display("*E Wrong length of first packet out from MAC");
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test_fail("Wrong length of first packet out from MAC");
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fail = fail + 1;
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fail = fail + 1;
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end
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end
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// checking first packet
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// checking first packet
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check_tx_packet((`MEMORY_BASE + i_data[1:0]), 0, (i_length), tmp);
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check_tx_packet((`MEMORY_BASE + i_data[1:0]), 0, (i_length), tmp);
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if (tmp > 0)
|
if (tmp > 0)
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begin
|
begin
|
test_fail("Wrong data of second transmitted packet");
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`TIME; $display("*E Wrong data of first transmitted packet");
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test_fail("Wrong data of first transmitted packet");
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fail = fail + 1;
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fail = fail + 1;
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end
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end
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// check first transmited TX packet CRC
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// check first transmited TX packet CRC
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check_tx_crc(0, (i_length), 1'b0, tmp); // length without CRC
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check_tx_crc(0, (i_length), 1'b0, tmp); // length without CRC
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if (tmp > 0)
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if (tmp > 0)
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begin
|
begin
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test_fail("Wrong CRC of second transmitted packet");
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`TIME; $display("*E Wrong CRC of first transmitted packet");
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test_fail("Wrong CRC of first transmitted packet");
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fail = fail + 1;
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fail = fail + 1;
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end
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end
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// check WB INT signal
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// check WB INT signal
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if (wb_int !== 1'b1)
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if (wb_int !== 1'b1)
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begin
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begin
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| Line 9891... |
Line 9898... |
begin
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begin
|
test_fail("WB INT signal should not be set");
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test_fail("WB INT signal should not be set");
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fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
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end
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end
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else
|
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begin
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// CHECK FIRST FRAME
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// check length of a first PACKET
|
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tmp_len = eth_phy.tx_len_err;
|
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#1;
|
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if (tmp_len != (num_of_frames + (4 - i_data)))
|
|
begin
|
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`TIME; $display("*E Wrong length of first packet out from MAC");
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test_fail("Wrong length of first packet out from MAC");
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fail = fail + 1;
|
|
end
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|
// checking first packet
|
|
check_tx_packet((`MEMORY_BASE + i_data[1:0]), 0, (num_of_frames), tmp);
|
|
if (tmp > 0)
|
|
begin
|
|
`TIME; $display("*E Wrong data of first transmitted packet");
|
|
test_fail("Wrong data of first transmitted packet");
|
|
fail = fail + 1;
|
|
end
|
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// check WB INT signal
|
|
if (wb_int !== 1'b1)
|
|
begin
|
|
`TIME; $display("*E WB INT signal should be set");
|
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test_fail("WB INT signal should be set");
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fail = fail + 1;
|
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end
|
|
// check TX buffer descriptor of a packet
|
|
check_tx_bd(num_of_bd, data);
|
|
if ( ((data[15:0] !== 16'h7900) && (num_of_bd == 1)) || // under-run, wrap bit
|
|
((data[15:0] !== 16'h5900) && (num_of_bd < 1)) ) // under-run, without wrap bit
|
|
begin
|
|
`TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
|
|
test_fail("TX buffer descriptor status is not correct");
|
|
fail = fail + 1;
|
|
end
|
|
// check interrupts
|
|
wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if ((data & `ETH_INT_TXE) !== 2'b10)
|
|
begin
|
|
`TIME; $display("*E Interrupt Transmit Error was not set, interrupt reg: %0h", data);
|
|
test_fail("Interrupt Transmit Buffer was not set");
|
|
fail = fail + 1;
|
|
end
|
|
if ((data & (~`ETH_INT_TXE)) !== 0)
|
|
begin
|
|
`TIME; $display("*E Other interrupts (except Transmit Error) were set, interrupt reg: %0h", data);
|
|
test_fail("Other interrupts (except Transmit Buffer) were set");
|
|
fail = fail + 1;
|
|
end
|
|
// clear interrupts
|
|
wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
// check WB INT signal
|
|
if (wb_int !== 1'b0)
|
|
begin
|
|
test_fail("WB INT signal should not be set");
|
|
fail = fail + 1;
|
|
end
|
|
end
|
num_of_bd = num_of_bd + 1;
|
num_of_bd = num_of_bd + 1;
|
// destination address on ethernet PHY
|
// destination address on ethernet PHY
|
eth_phy.set_tx_mem_addr(0);
|
eth_phy.set_tx_mem_addr(0);
|
// WAIT FOR FIRST TRANSMIT
|
// WAIT FOR SECOND TRANSMIT
|
check_tx_bd(num_of_bd, data);
|
check_tx_bd(num_of_bd, data);
|
wait (MTxEn === 1'b1); // start first transmit
|
wait (MTxEn === 1'b1); // start first transmit
|
if (data[15] !== 1)
|
if (data[15] !== 1)
|
begin
|
begin
|
test_fail("Wrong buffer descriptor's ready bit read out from MAC");
|
test_fail("Wrong buffer descriptor's ready bit read out from MAC");
|
| Line 9911... |
Line 9977... |
@(posedge wb_clk);
|
@(posedge wb_clk);
|
end
|
end
|
repeat (1) @(posedge wb_clk);
|
repeat (1) @(posedge wb_clk);
|
// CHECK SECOND FRAME
|
// CHECK SECOND FRAME
|
// check length of a second PACKET
|
// check length of a second PACKET
|
|
if (frame_ended == 1'b1)
|
|
begin
|
|
`TIME; $display(" Second frame after under-run ended");
|
|
end
|
tmp_len = eth_phy.tx_len;
|
tmp_len = eth_phy.tx_len;
|
#1;
|
#1;
|
if (tmp_len != (i_length + 4))
|
if (tmp_len != (i_length + 4))
|
begin
|
begin
|
|
`TIME; $display("*E Wrong length of second packet out from MAC");
|
test_fail("Wrong length of second packet out from MAC");
|
test_fail("Wrong length of second packet out from MAC");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
// checking second packet
|
// checking second packet
|
check_tx_packet(`MEMORY_BASE, 0, (i_length), tmp);
|
check_tx_packet(`MEMORY_BASE, 0, (i_length), tmp);
|
if (tmp > 0)
|
if (tmp > 0)
|
begin
|
begin
|
|
`TIME; $display("*E Wrong data of second transmitted packet");
|
test_fail("Wrong data of second transmitted packet");
|
test_fail("Wrong data of second transmitted packet");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
// check second transmited TX packet CRC
|
// check second transmited TX packet CRC
|
check_tx_crc(0, (i_length), 1'b0, tmp); // length without CRC
|
check_tx_crc(0, (i_length), 1'b0, tmp); // length without CRC
|
if (tmp > 0)
|
if (tmp > 0)
|
begin
|
begin
|
|
`TIME; $display("*E Wrong CRC of second transmitted packet");
|
test_fail("Wrong CRC of second transmitted packet");
|
test_fail("Wrong CRC of second transmitted packet");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
// check WB INT signal
|
// check WB INT signal
|
if (wb_int !== 1'b1)
|
if (wb_int !== 1'b1)
|
| Line 9976... |
Line 10049... |
i_data = i_data - 1;
|
i_data = i_data - 1;
|
// the number of frame transmitted
|
// the number of frame transmitted
|
num_of_frames = num_of_frames + 1;
|
num_of_frames = num_of_frames + 1;
|
num_of_bd = 0;
|
num_of_bd = 0;
|
// set length (LOOP variable)
|
// set length (LOOP variable)
|
if (num_of_frames == i_length + 4) // 64 => this vas last Byte (1st .. 64th) when i_length = min_tmp - 4
|
if (num_of_frames == i_length + 4) // 64 => this was last Byte (1st .. 64th) when i_length = min_tmp - 4
|
i_length = (max_tmp - 4);
|
i_length = (max_tmp - 4);
|
@(posedge wb_clk);
|
@(posedge wb_clk);
|
end
|
end
|
// disable TX
|
// disable TX
|
wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
|
wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
|
| Line 10473... |
Line 10546... |
// unmask interrupts
|
// unmask interrupts
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
|
`ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
`ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
// set all buffer descriptors to TX - must be set before RX enable
|
// set all buffer descriptors to TX - must be set before RX enable
|
wbm_write(`ETH_TX_BD_NUM, 32'h80, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_write(`ETH_TX_BD_NUM, 32'h80, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
// enable RX, set full-duplex mode, padding and CRC appending
|
// enable RX, set full-duplex mode, receive small, NO correct IFG
|
wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
|
wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
|
`ETH_MODER_PRO | `ETH_MODER_BRO,
|
`ETH_MODER_PRO | `ETH_MODER_BRO,
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
|
// write to phy's control register for 10Mbps
|
// write to phy's control register for 10Mbps
|
| Line 10558... |
Line 10631... |
// unmask interrupts
|
// unmask interrupts
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
|
wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
|
`ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
`ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
// set all buffer descriptors to TX - must be set before RX enable
|
// set all buffer descriptors to TX - must be set before RX enable
|
wbm_write(`ETH_TX_BD_NUM, 32'h80, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_write(`ETH_TX_BD_NUM, 32'h80, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
// enable RX, set full-duplex mode, padding and CRC appending
|
// enable RX, set full-duplex mode, receive small, NO correct IFG
|
wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
|
wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
|
`ETH_MODER_PRO | `ETH_MODER_BRO,
|
`ETH_MODER_PRO | `ETH_MODER_BRO,
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
|
// write to phy's control register for 100Mbps
|
// write to phy's control register for 100Mbps
|
