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//////////////////////////////////////////////////////////////////////

//////////////////////////////////////////////////////////////////////

//

//

// CVS Revision History

// CVS Revision History

//

//

// $Log: not supported by cvs2svn $

// $Log: not supported by cvs2svn $

// Revision 1.24  2002/11/22 17:29:42  mohor

// Revision 1.24  2002/11/22 17:29:42  mohor

// Flow control test almost finished.

// Flow control test almost finished.

//

//

// Revision 1.23  2002/11/22 02:12:16  mohor

// Revision 1.23  2002/11/22 02:12:16  mohor

// test_mac_full_duplex_flow_control tests pretty much finished.

// test_mac_full_duplex_flow_control tests pretty much finished.

// Generating wb_clk clock

// Generating wb_clk clock

initial

initial

begin

begin

  wb_clk=0;

  wb_clk=0;

//  forever #2.5 wb_clk = ~wb_clk;  // 2*2.5 ns -> 200.0 MHz    

//  forever #2.5 wb_clk = ~wb_clk;  // 2*2.5 ns -> 200.0 MHz    

//  forever #10 wb_clk = ~wb_clk;  // 2*10 ns -> 50.0 MHz    

//  forever #10 wb_clk = ~wb_clk;  // 2*10 ns -> 50.0 MHz    

//  forever #12.5 wb_clk = ~wb_clk;  // 2*12.5 ns -> 40 MHz    

//  forever #12.5 wb_clk = ~wb_clk;  // 2*12.5 ns -> 40 MHz    

//  forever #20 wb_clk = ~wb_clk;  // 2*20 ns -> 25 MHz    

//  forever #20 wb_clk = ~wb_clk;  // 2*20 ns -> 25 MHz    

//  forever #25 wb_clk = ~wb_clk;  // 2*25 ns -> 20.0 MHz

//  forever #25 wb_clk = ~wb_clk;  // 2*25 ns -> 20.0 MHz

//  forever #31.25 wb_clk = ~wb_clk;  // 2*31.25 ns -> 16.0 MHz    

//  forever #31.25 wb_clk = ~wb_clk;  // 2*31.25 ns -> 16.0 MHz    

//  forever #50 wb_clk = ~wb_clk;  // 2*50 ns -> 10.0 MHz

//  forever #50 wb_clk = ~wb_clk;  // 2*50 ns -> 10.0 MHz

//  forever #55 wb_clk = ~wb_clk;  // 2*55 ns ->  9.1 MHz    

//  forever #55 wb_clk = ~wb_clk;  // 2*55 ns ->  9.1 MHz    

reg   [3:0]  wbm_init_waits; // initial wait cycles between CYC_O and STB_O of WB Master

reg   [3:0]  wbm_init_waits; // initial wait cycles between CYC_O and STB_O of WB Master

reg   [3:0]  wbm_subseq_waits; // subsequent wait cycles between STB_Os of WB Master

reg   [3:0]  wbm_subseq_waits; // subsequent wait cycles between STB_Os of WB Master

reg   [2:0]  wbs_waits; // wait cycles befor WB Slave responds

reg   [2:0]  wbs_waits; // wait cycles befor WB Slave responds

reg   [7:0]  wbs_retries; // if RTY response, then this is the number of retries before ACK

reg   [7:0]  wbs_retries; // if RTY response, then this is the number of retries before ACK

initial

initial

begin

begin

  wait(StartTB);  // Start of testbench

  wait(StartTB);  // Start of testbench

  // Initial global values

  // Initial global values

  tests_successfull = 0;

  tests_successfull = 0;

  tests_failed = 0;

  tests_failed = 0;

  wbm_init_waits = 4'h1;

  wbm_init_waits = 4'h1;

  wbm_subseq_waits = 4'h3;

  wbm_subseq_waits = 4'h3;

  wbs_waits = 4'h1;

  wbs_waits = 4'h1;

  wbs_retries = 8'h2;

  wbs_retries = 8'h2;

  wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);

  wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);

  //  Call tests

  //  Call tests

  //  ----------

  //  ----------

//    test_mii(0, 17);                        // 0 - 17

//    test_mii(0, 17);                        // 0 - 17

  test_note("PHY generates ideal Carrier sense and Collision signals for following tests");

  test_note("PHY generates ideal Carrier sense and Collision signals for following tests");

  eth_phy.carrier_sense_real_delay(0);

  eth_phy.carrier_sense_real_delay(0);

  test_note("PHY generates 'real delayed' Carrier sense and Collision signals for following tests");

  test_note("PHY generates 'real delayed' Carrier sense and Collision signals for following tests");

  eth_phy.carrier_sense_real_delay(1);

  eth_phy.carrier_sense_real_delay(1);

fail = 0;

fail = 0;

// reset MAC registers

// reset MAC registers

hard_reset;

hard_reset;

// reset MAC and MII LOGIC with soft reset

// reset MAC and MII LOGIC with soft reset

//////////////////////////////////////////////////////////////////////

//////////////////////////////////////////////////////////////////////

////                                                              ////

////                                                              ////

////  test_access_to_mac_reg:                                     ////

////  test_access_to_mac_reg:                                     ////

                if ( (addr == `ETH_MIICOMMAND) && (i_data <= 2) ) // DO NOT WRITE to 3 LSBits of MIICOMMAND !!!

                if ( (addr == `ETH_MIICOMMAND) && (i_data <= 2) ) // DO NOT WRITE to 3 LSBits of MIICOMMAND !!!

                  ;

                  ;

                else

                else

                  begin

                  begin

                    wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);

                    wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);

                    wbm_read(addr, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);

                    wbm_read(addr, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);

                    if ( ((i_data >= bit_start_1) && (i_data <= bit_end_1)) ||

                    if ( ((i_data >= bit_start_1) && (i_data <= bit_end_1)) ||

                         ((i_data >= bit_start_2) && (i_data <= bit_end_2)) ) // data should be equal to tmp_data

                         ((i_data >= bit_start_2) && (i_data <= bit_end_2)) ) // data should be equal to tmp_data

                      begin

                      begin

                        if (tmp_data !== data)

                        if (tmp_data !== data)

        endcase

        endcase

        wbm_init_waits = {$random} % 3;

        wbm_init_waits = {$random} % 3;

        wbm_subseq_waits = {$random} % 5; // it is not important for single accesses

        wbm_subseq_waits = {$random} % 5; // it is not important for single accesses

        if (i == 0)

        if (i == 0)

          wbm_write(addr, ~data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);

          wbm_write(addr, ~data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);

        else if (i == 2)

        else if (i == 2)

          wbm_write(addr, 32'hFFFFFFFF, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);

          wbm_write(addr, 32'hFFFFFFFF, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);

        else if ((i == 1) || (i == 4))

        else if ((i == 1) || (i == 4))

        begin

        begin

          wbm_read(addr, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);

          wbm_read(addr, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);

          if (tmp_data !== data)

          if (tmp_data !== data)

          begin

          begin

    $display("  TEST 3: BUFFER DESC. RAM PRESERVING VALUES AFTER HARD RESET OF THE MAC AND RESETING THE LOGIC");

    $display("  TEST 3: BUFFER DESC. RAM PRESERVING VALUES AFTER HARD RESET OF THE MAC AND RESETING THE LOGIC");

    // reset MAC registers

    // reset MAC registers

    hard_reset;

    hard_reset;

    // reset LOGIC with soft reset

    // reset LOGIC with soft reset

    for (i = 0; i <= 3; i = i + 1) // 0, 2 - WRITE; 1, 3 - READ

    for (i = 0; i <= 3; i = i + 1) // 0, 2 - WRITE; 1, 3 - READ

    begin

    begin

      for (i_addr = 32'h400; i_addr <= 32'h7FC; i_addr = i_addr + 4) // buffer descriptor address

      for (i_addr = 32'h400; i_addr <= 32'h7FC; i_addr = i_addr + 4) // buffer descriptor address

      begin

      begin

        addr = `ETH_BASE + i_addr;

        addr = `ETH_BASE + i_addr;

      if ((i == 0) || (i == 2))

      if ((i == 0) || (i == 2))

      begin

      begin

        // reset MAC registers

        // reset MAC registers

        hard_reset;

        hard_reset;

        // reset LOGIC with soft reset

        // reset LOGIC with soft reset

      end

      end

    end

    end

    if(fail == 0)

    if(fail == 0)

      test_ok;

      test_ok;

    else

    else

fail = 0;

fail = 0;

// reset MAC registers

// reset MAC registers

hard_reset;

hard_reset;

// reset MAC and MII LOGIC with soft reset

// reset MAC and MII LOGIC with soft reset

//////////////////////////////////////////////////////////////////////

//////////////////////////////////////////////////////////////////////

////                                                              ////

////                                                              ////

////  test_mii:                                                   ////

////  test_mii:                                                   ////

    begin

    begin

      // read request

      // read request

      #Tp mii_read_req(phy_addr, reg_addr);

      #Tp mii_read_req(phy_addr, reg_addr);

      check_mii_busy; // wait for read to finish

      check_mii_busy; // wait for read to finish

      // read data

      // read data

      if (phy_data !== 16'hDEAD)

      if (phy_data !== 16'hDEAD)

      begin

      begin

        test_fail("Wrong data was read from PHY from 'not used' address space");

        test_fail("Wrong data was read from PHY from 'not used' address space");

        fail = fail + 1;

        fail = fail + 1;

      end

      end

    reg_addr = 5'h3;

    reg_addr = 5'h3;

    // read request

    // read request

    #Tp mii_read_req(phy_addr, reg_addr);

    #Tp mii_read_req(phy_addr, reg_addr);

    check_mii_busy; // wait for read to finish

    check_mii_busy; // wait for read to finish

    // read data

    // read data

    if (phy_data !== {`PHY_ID2, `MAN_MODEL_NUM, `MAN_REVISION_NUM})

    if (phy_data !== {`PHY_ID2, `MAN_MODEL_NUM, `MAN_REVISION_NUM})

    begin

    begin

      test_fail("Wrong data was read from PHY from ID register 2");

      test_fail("Wrong data was read from PHY from ID register 2");

      fail = fail + 1;

      fail = fail + 1;

    end

    end

    check_mii_busy; // wait for write to finish

    check_mii_busy; // wait for write to finish

    // read request

    // read request

    #Tp mii_read_req(phy_addr, reg_addr);

    #Tp mii_read_req(phy_addr, reg_addr);

    check_mii_busy; // wait for read to finish

    check_mii_busy; // wait for read to finish

    // read data

    // read data

    if (tmp_data !== phy_data)

    if (tmp_data !== phy_data)

    begin

    begin

      test_fail("Data was written into unwritable PHY register - ID register 2");

      test_fail("Data was written into unwritable PHY register - ID register 2");

      fail = fail + 1;

      fail = fail + 1;

    end

    end

    reg_addr = 5'h0; // control register

    reg_addr = 5'h0; // control register

    // read request

    // read request

    #Tp mii_read_req(phy_addr, reg_addr);

    #Tp mii_read_req(phy_addr, reg_addr);

    check_mii_busy; // wait for read to finish

    check_mii_busy; // wait for read to finish

    // read data

    // read data

    // write request

    // write request

    phy_data = 16'h7DFF; // bit 15 (RESET bit) and bit 9 are self clearing bits

    phy_data = 16'h7DFF; // bit 15 (RESET bit) and bit 9 are self clearing bits

    #Tp mii_write_req(phy_addr, reg_addr, phy_data);

    #Tp mii_write_req(phy_addr, reg_addr, phy_data);

    check_mii_busy; // wait for write to finish

    check_mii_busy; // wait for write to finish

    // read request

    // read request

    #Tp mii_read_req(phy_addr, reg_addr);

    #Tp mii_read_req(phy_addr, reg_addr);

    check_mii_busy; // wait for read to finish

    check_mii_busy; // wait for read to finish

    // read data

    // read data

    if (phy_data !== 16'h7DFF)

    if (phy_data !== 16'h7DFF)

    begin

    begin

      test_fail("Data was not correctly written into OR read from writable PHY register - control register");

      test_fail("Data was not correctly written into OR read from writable PHY register - control register");

      fail = fail + 1;

      fail = fail + 1;

    end

    end

    check_mii_busy; // wait for write to finish

    check_mii_busy; // wait for write to finish

    // read request

    // read request

    #Tp mii_read_req(phy_addr, reg_addr);

    #Tp mii_read_req(phy_addr, reg_addr);

    check_mii_busy; // wait for read to finish

    check_mii_busy; // wait for read to finish

    // read data

    // read data

    if (phy_data !== tmp_data)

    if (phy_data !== tmp_data)

    begin

    begin

      test_fail("Data was not correctly written into OR read from writable PHY register - control register");

      test_fail("Data was not correctly written into OR read from writable PHY register - control register");

      fail = fail + 1;

      fail = fail + 1;

    end

    end

    check_mii_busy; // wait for write to finish

    check_mii_busy; // wait for write to finish

    // read request

    // read request

    #Tp mii_read_req(phy_addr, reg_addr);

    #Tp mii_read_req(phy_addr, reg_addr);

    check_mii_busy; // wait for read to finish

    check_mii_busy; // wait for read to finish

    // read data

    // read data

    if (phy_data !== tmp_data)

    if (phy_data !== tmp_data)

    begin

    begin

      test_fail("Data was not correctly written into OR read from writable PHY register - control register");

      test_fail("Data was not correctly written into OR read from writable PHY register - control register");

      fail = fail + 1;

      fail = fail + 1;

    end

    end

    check_mii_busy; // wait for write to finish

    check_mii_busy; // wait for write to finish

    // read request

    // read request

    #Tp mii_read_req(phy_addr, reg_addr);

    #Tp mii_read_req(phy_addr, reg_addr);

    check_mii_busy; // wait for read to finish

    check_mii_busy; // wait for read to finish

    // read data

    // read data

    // check self clearing of reset bit

    // check self clearing of reset bit

    if (tmp_data[15] !== 1'b0)

    if (tmp_data[15] !== 1'b0)

    begin

    begin

      test_fail("Reset bit should be self cleared - control register");

      test_fail("Reset bit should be self cleared - control register");

      fail = fail + 1;

      fail = fail + 1;

        check_mii_busy; // wait for write to finish

        check_mii_busy; // wait for write to finish

        // read request

        // read request

        #Tp mii_read_req(phy_addr, reg_addr);

        #Tp mii_read_req(phy_addr, reg_addr);

        check_mii_busy; // wait for read to finish

        check_mii_busy; // wait for read to finish

        // read data

        // read data

        #Tp;

        #Tp;

        if (phy_data !== tmp_data)

        if (phy_data !== tmp_data)

        begin

        begin

          if (i)

          if (i)

            test_fail("Data was not correctly written into OR read from test registers (without preamble)");

            test_fail("Data was not correctly written into OR read from test registers (without preamble)");

        check_mii_busy; // wait for write to finish

        check_mii_busy; // wait for write to finish

        // read request

        // read request

        #Tp mii_read_req(phy_addr, reg_addr);

        #Tp mii_read_req(phy_addr, reg_addr);

        check_mii_busy; // wait for read to finish

        check_mii_busy; // wait for read to finish

        // read data

        // read data

        #Tp;

        #Tp;

        if (phy_data !== tmp_data)

        if (phy_data !== tmp_data)

        begin

        begin

          if (i)

          if (i)

            test_fail("Data was not correctly written into OR read from test registers (without preamble)");

            test_fail("Data was not correctly written into OR read from test registers (without preamble)");

        check_mii_busy; // wait for write to finish

        check_mii_busy; // wait for write to finish

        // read request

        // read request

        #Tp mii_read_req(phy_addr, reg_addr);

        #Tp mii_read_req(phy_addr, reg_addr);

        check_mii_busy; // wait for read to finish

        check_mii_busy; // wait for read to finish

        // read data

        // read data

        #Tp;

        #Tp;

        if (phy_data !== tmp_data)

        if (phy_data !== tmp_data)

        begin

        begin

          if (i)

          if (i)

            test_fail("Data was not correctly written into OR read from test registers (without preamble)");

            test_fail("Data was not correctly written into OR read from test registers (without preamble)");

    // read request

    // read request

    #Tp mii_read_req(phy_addr, reg_addr);

    #Tp mii_read_req(phy_addr, reg_addr);

    check_mii_busy; // wait for read to finish

    check_mii_busy; // wait for read to finish

    // read data

    // read data

    $display("  => Two errors will be displayed from WB Bus Monitor, because correct HIGH Z data was read");

    $display("  => Two errors will be displayed from WB Bus Monitor, because correct HIGH Z data was read");

    if (tmp_data !== 16'hzzzz)

    if (tmp_data !== 16'hzzzz)

    begin

    begin

      test_fail("Data was read from PHY register with wrong PHY address - control register");

      test_fail("Data was read from PHY register with wrong PHY address - control register");

      fail = fail + 1;

      fail = fail + 1;

    end

    end

    phy_addr = 5'h1; // correct PHY address

    phy_addr = 5'h1; // correct PHY address

    // read request

    // read request

    #Tp mii_read_req(phy_addr, reg_addr);

    #Tp mii_read_req(phy_addr, reg_addr);

    check_mii_busy; // wait for read to finish

    check_mii_busy; // wait for read to finish

    // read data

    // read data

    if (phy_data === tmp_data)

    if (phy_data === tmp_data)

    begin

    begin

      test_fail("Data was written into PHY register with wrong PHY address - control register");

      test_fail("Data was written into PHY register with wrong PHY address - control register");

      fail = fail + 1;

      fail = fail + 1;

    end

    end

            @(posedge Mdc_O);

            @(posedge Mdc_O);

            // read request

            // read request

            #Tp mii_read_req(phy_addr, reg_addr);

            #Tp mii_read_req(phy_addr, reg_addr);

            check_mii_busy; // wait for read to finish

            check_mii_busy; // wait for read to finish

            // read and check data

            // read and check data

            if (phy_data !== tmp_data)

            if (phy_data !== tmp_data)

            begin

            begin

              test_fail("Data was not correctly written into OR read from PHY register - control register");

              test_fail("Data was not correctly written into OR read from PHY register - control register");

              fail = fail + 1;

              fail = fail + 1;

            end

            end

              #Tp cnt = cnt + 1;

              #Tp cnt = cnt + 1;

            end

            end

            @(posedge Mdc_O);

            @(posedge Mdc_O);

            check_mii_busy; // wait for read to finish

            check_mii_busy; // wait for read to finish

            // read and check data

            // read and check data

            if (phy_data !== tmp_data)

            if (phy_data !== tmp_data)

            begin

            begin

              test_fail("Data was not correctly written into OR read from PHY register - control register");

              test_fail("Data was not correctly written into OR read from PHY register - control register");

              fail = fail + 1;

              fail = fail + 1;

            end

            end

            @(posedge Mdc_O);

            @(posedge Mdc_O);

            // read request

            // read request

            #Tp mii_read_req(phy_addr, reg_addr);

            #Tp mii_read_req(phy_addr, reg_addr);

            check_mii_busy; // wait for read to finish

            check_mii_busy; // wait for read to finish

            // read and check data

            // read and check data

            if (phy_data !== tmp_data)

            if (phy_data !== tmp_data)

            begin

            begin

              test_fail("Data was not correctly written into OR read from PHY register - control register");

              test_fail("Data was not correctly written into OR read from PHY register - control register");

              fail = fail + 1;

              fail = fail + 1;

            end

            end

              #Tp cnt = cnt + 1;

              #Tp cnt = cnt + 1;

            end

            end

            @(posedge Mdc_O);

            @(posedge Mdc_O);

            check_mii_busy; // wait for read to finish

            check_mii_busy; // wait for read to finish

            // read and check data

            // read and check data

            if (phy_data !== tmp_data)

            if (phy_data !== tmp_data)

            begin

            begin

              test_fail("Data was not correctly written into OR read from PHY register - control register");

              test_fail("Data was not correctly written into OR read from PHY register - control register");

              fail = fail + 1;

              fail = fail + 1;

            end

            end

                4'hF, 1, wbm_init_waits, wbm_subseq_waits);

                4'hF, 1, wbm_init_waits, wbm_subseq_waits);

      @(posedge Mdc_O);

      @(posedge Mdc_O);

      // write request

      // write request

      #Tp mii_write_req(phy_addr, reg_addr, 16'h5A5A);

      #Tp mii_write_req(phy_addr, reg_addr, 16'h5A5A);

      // read data from MII status register - Busy and Nvalid bits

      // read data from MII status register - Busy and Nvalid bits

      // check MII IO signal and Busy and Nvalid bits

      // check MII IO signal and Busy and Nvalid bits

      if (Mdio_IO !== 1'bz) // Mdio_IO should be HIGH Z here - testbench selfcheck

      if (Mdio_IO !== 1'bz) // Mdio_IO should be HIGH Z here - testbench selfcheck

      begin

      begin

        test_fail("Testbench error - read was to late, Mdio_IO is not HIGH Z - set higher clock divider");

        test_fail("Testbench error - read was to late, Mdio_IO is not HIGH Z - set higher clock divider");

      else

      else

      begin

      begin

        repeat(64) @(posedge Mdc_O);

        repeat(64) @(posedge Mdc_O);

      end

      end

      // read data from MII status register - Busy and Nvalid bits

      // read data from MII status register - Busy and Nvalid bits

      // check MII IO signal and Busy and Nvalid bits

      // check MII IO signal and Busy and Nvalid bits

      if (Mdio_IO === 1'bz) // Mdio_IO should not be HIGH Z here - testbench selfcheck

      if (Mdio_IO === 1'bz) // Mdio_IO should not be HIGH Z here - testbench selfcheck

      begin

      begin

        test_fail("Testbench error - read was to late, Mdio_IO is HIGH Z - set higher clock divider");

        test_fail("Testbench error - read was to late, Mdio_IO is HIGH Z - set higher clock divider");

      end

      end

      // wait for next negative clock edge

      // wait for next negative clock edge

      @(negedge Mdc_O);

      @(negedge Mdc_O);

      // read data from MII status register - Busy and Nvalid bits

      // read data from MII status register - Busy and Nvalid bits

      // check MII IO signal and Busy and Nvalid bits

      // check MII IO signal and Busy and Nvalid bits

      if (Mdio_IO !== 1'bz) // Mdio_IO should be HIGH Z here - testbench selfcheck

      if (Mdio_IO !== 1'bz) // Mdio_IO should be HIGH Z here - testbench selfcheck

      begin

      begin

        test_fail("Testbench error - read was to early, Mdio_IO is not HIGH Z - set higher clock divider");

        test_fail("Testbench error - read was to early, Mdio_IO is not HIGH Z - set higher clock divider");

      while (i1 <= 2)

      while (i1 <= 2)

      begin

      begin

        // wait for next positive clock edge

        // wait for next positive clock edge

        @(posedge Mdc_O);

        @(posedge Mdc_O);

        // read data from MII status register - Busy and Nvalid bits

        // read data from MII status register - Busy and Nvalid bits

        // check MII IO signal and Busy and Nvalid bits

        // check MII IO signal and Busy and Nvalid bits

        if (Mdio_IO !== 1'bz) // Mdio_IO should be HIGH Z here - testbench selfcheck

        if (Mdio_IO !== 1'bz) // Mdio_IO should be HIGH Z here - testbench selfcheck

        begin

        begin

          test_fail("Testbench error - read was to early, Mdio_IO is not HIGH Z - set higher clock divider");

          test_fail("Testbench error - read was to early, Mdio_IO is not HIGH Z - set higher clock divider");

                4'hF, 1, wbm_init_waits, wbm_subseq_waits);

                4'hF, 1, wbm_init_waits, wbm_subseq_waits);

      @(posedge Mdc_O);

      @(posedge Mdc_O);

      // read request

      // read request

      #Tp mii_read_req(phy_addr, reg_addr);

      #Tp mii_read_req(phy_addr, reg_addr);

      // read data from MII status register - Busy and Nvalid bits

      // read data from MII status register - Busy and Nvalid bits

      // check MII IO signal and Busy and Nvalid bits

      // check MII IO signal and Busy and Nvalid bits

      if (Mdio_IO !== 1'bz) // Mdio_IO should be HIGH Z here - testbench selfcheck

      if (Mdio_IO !== 1'bz) // Mdio_IO should be HIGH Z here - testbench selfcheck

      begin

      begin

        test_fail("Testbench error - read was to late, Mdio_IO is not HIGH Z - set higher clock divider");

        test_fail("Testbench error - read was to late, Mdio_IO is not HIGH Z - set higher clock divider");

        repeat(63) @(posedge Mdc_O);

        repeat(63) @(posedge Mdc_O);

      end

      end

      // wait for next negative clock edge

      // wait for next negative clock edge

      @(negedge Mdc_O);

      @(negedge Mdc_O);

      // read data from MII status register - Busy and Nvalid bits

      // read data from MII status register - Busy and Nvalid bits

      // check MII IO signal and Busy and Nvalid bits

      // check MII IO signal and Busy and Nvalid bits

      if (Mdio_IO === 1'bz) // Mdio_IO should not be HIGH Z here - testbench selfcheck

      if (Mdio_IO === 1'bz) // Mdio_IO should not be HIGH Z here - testbench selfcheck

      begin

      begin

        test_fail("Testbench error - read was to late, Mdio_IO is HIGH Z - set higher clock divider");

        test_fail("Testbench error - read was to late, Mdio_IO is HIGH Z - set higher clock divider");

      end

      end

      // wait for next positive clock edge

      // wait for next positive clock edge

      @(posedge Mdc_O);

      @(posedge Mdc_O);

      // read data from MII status register - Busy and Nvalid bits

      // read data from MII status register - Busy and Nvalid bits

      // check MII IO signal and Busy and Nvalid bits

      // check MII IO signal and Busy and Nvalid bits

      if (Mdio_IO !== 1'bz) // Mdio_IO should be HIGH Z here - testbench selfcheck

      if (Mdio_IO !== 1'bz) // Mdio_IO should be HIGH Z here - testbench selfcheck

      begin

      begin

        test_fail("Testbench error - read was to early, Mdio_IO is not HIGH Z - set higher clock divider");

        test_fail("Testbench error - read was to early, Mdio_IO is not HIGH Z - set higher clock divider");

      while (i1 <= 2)

      while (i1 <= 2)

      begin

      begin

        // wait for next positive clock edge

        // wait for next positive clock edge

        @(posedge Mdc_O);

        @(posedge Mdc_O);

        // read data from MII status register - Busy and Nvalid bits

        // read data from MII status register - Busy and Nvalid bits

        // check MII IO signal and Busy and Nvalid bits

        // check MII IO signal and Busy and Nvalid bits

        if (Mdio_IO !== 1'bz) // Mdio_IO should be HIGH Z here - testbench selfcheck

        if (Mdio_IO !== 1'bz) // Mdio_IO should be HIGH Z here - testbench selfcheck

        begin

        begin

          test_fail("Testbench error - read was to early, Mdio_IO is not HIGH Z - set higher clock divider");

          test_fail("Testbench error - read was to early, Mdio_IO is not HIGH Z - set higher clock divider");

                4'hF, 1, wbm_init_waits, wbm_subseq_waits);

                4'hF, 1, wbm_init_waits, wbm_subseq_waits);

      @(posedge Mdc_O);

      @(posedge Mdc_O);

      // scan request

      // scan request

      #Tp mii_scan_req(phy_addr, reg_addr);

      #Tp mii_scan_req(phy_addr, reg_addr);

      // read data from MII status register - Busy and Nvalid bits

      // read data from MII status register - Busy and Nvalid bits

      // check MII IO signal and Busy and Nvalid bits

      // check MII IO signal and Busy and Nvalid bits

      if (Mdio_IO !== 1'bz) // Mdio_IO should be HIGH Z here - testbench selfcheck

      if (Mdio_IO !== 1'bz) // Mdio_IO should be HIGH Z here - testbench selfcheck

      begin

      begin

        test_fail("Testbench error - read was to late, Mdio_IO is not HIGH Z - set higher clock divider");

        test_fail("Testbench error - read was to late, Mdio_IO is not HIGH Z - set higher clock divider");

      #Tp mii_scan_finish; // finish scan operation

      #Tp mii_scan_finish; // finish scan operation

      // wait for next positive clock edge

      // wait for next positive clock edge

      repeat(10) @(posedge Mdc_O);

      repeat(10) @(posedge Mdc_O);

      // read data from MII status register - Busy and Nvalid bits

      // read data from MII status register - Busy and Nvalid bits

      // check MII IO signal and Busy and Nvalid bits

      // check MII IO signal and Busy and Nvalid bits

      if (Mdio_IO === 1'bz) // Mdio_IO should not be HIGH Z here - testbench selfcheck

      if (Mdio_IO === 1'bz) // Mdio_IO should not be HIGH Z here - testbench selfcheck

      begin

      begin

        test_fail("Testbench error - read was to late, Mdio_IO is HIGH Z - set higher clock divider");

        test_fail("Testbench error - read was to late, Mdio_IO is HIGH Z - set higher clock divider");

      end

      end

      // wait for next negative clock edge

      // wait for next negative clock edge

      @(negedge Mdc_O);

      @(negedge Mdc_O);

      // read data from MII status register - Busy and Nvalid bits

      // read data from MII status register - Busy and Nvalid bits

      // check MII IO signal and Busy and Nvalid bits

      // check MII IO signal and Busy and Nvalid bits

      if (Mdio_IO === 1'bz) // Mdio_IO should not be HIGH Z here - testbench selfcheck

      if (Mdio_IO === 1'bz) // Mdio_IO should not be HIGH Z here - testbench selfcheck

      begin

      begin

        test_fail("Testbench error - read was to late, Mdio_IO is HIGH Z - set higher clock divider");

        test_fail("Testbench error - read was to late, Mdio_IO is HIGH Z - set higher clock divider");

      end

      end

      // wait for next negative clock edge

      // wait for next negative clock edge

      @(posedge Mdc_O);

      @(posedge Mdc_O);

      // read data from MII status register - Busy and Nvalid bits

      // read data from MII status register - Busy and Nvalid bits

      // check MII IO signal and Busy and Nvalid bits

      // check MII IO signal and Busy and Nvalid bits

      if (Mdio_IO !== 1'bz) // Mdio_IO should be HIGH Z here - testbench selfcheck

      if (Mdio_IO !== 1'bz) // Mdio_IO should be HIGH Z here - testbench selfcheck

      begin

      begin

        test_fail("Testbench error - read was to early, Mdio_IO is not HIGH Z - set higher clock divider");

        test_fail("Testbench error - read was to early, Mdio_IO is not HIGH Z - set higher clock divider");

      while ((i1 <= 2) || (i2 == 0))

      while ((i1 <= 2) || (i2 == 0))

      begin

      begin

        // wait for next positive clock edge

        // wait for next positive clock edge

        @(posedge Mdc_O);

        @(posedge Mdc_O);

        // read data from MII status register - Busy and Nvalid bits

        // read data from MII status register - Busy and Nvalid bits

        // check MII IO signal and Busy and Nvalid bits

        // check MII IO signal and Busy and Nvalid bits

        if (Mdio_IO !== 1'bz) // Mdio_IO should be HIGH Z here - testbench selfcheck

        if (Mdio_IO !== 1'bz) // Mdio_IO should be HIGH Z here - testbench selfcheck

        begin

        begin

          test_fail("Testbench error - read was to early, Mdio_IO is not HIGH Z - set higher clock divider");