| Line 40... |
Line 40... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.30 2003/10/17 07:45:17 markom
|
|
// mbist signals updated according to newest convention
|
|
//
|
// Revision 1.29 2003/08/20 12:06:24 mohor
|
// Revision 1.29 2003/08/20 12:06:24 mohor
|
// Artisan RAMs added.
|
// Artisan RAMs added.
|
//
|
//
|
// Revision 1.28 2003/01/31 15:58:27 mohor
|
// Revision 1.28 2003/01/31 15:58:27 mohor
|
// Tests test_mac_full_duplex_receive 4-7 fixed to proper BD.
|
// Tests test_mac_full_duplex_receive 4-7 fixed to proper BD.
|
| Line 178... |
Line 181... |
// Ethernet Master Interface signals
|
// Ethernet Master Interface signals
|
wire [31:0] eth_ma_wb_adr_o, eth_ma_wb_dat_i, eth_ma_wb_dat_o;
|
wire [31:0] eth_ma_wb_adr_o, eth_ma_wb_dat_i, eth_ma_wb_dat_o;
|
wire [3:0] eth_ma_wb_sel_o;
|
wire [3:0] eth_ma_wb_sel_o;
|
wire eth_ma_wb_we_o, eth_ma_wb_cyc_o, eth_ma_wb_stb_o, eth_ma_wb_ack_i, eth_ma_wb_err_i;
|
wire eth_ma_wb_we_o, eth_ma_wb_cyc_o, eth_ma_wb_stb_o, eth_ma_wb_ack_i, eth_ma_wb_err_i;
|
|
|
|
wire [2:0] eth_ma_wb_cti_o;
|
|
wire [1:0] eth_ma_wb_bte_o;
|
|
|
|
|
// Connecting Ethernet top module
|
// Connecting Ethernet top module
|
eth_top eth_top
|
eth_top eth_top
|
(
|
(
|
| Line 197... |
Line 201... |
// WISHBONE master
|
// WISHBONE master
|
.m_wb_adr_o(eth_ma_wb_adr_o), .m_wb_sel_o(eth_ma_wb_sel_o), .m_wb_we_o(eth_ma_wb_we_o),
|
.m_wb_adr_o(eth_ma_wb_adr_o), .m_wb_sel_o(eth_ma_wb_sel_o), .m_wb_we_o(eth_ma_wb_we_o),
|
.m_wb_dat_i(eth_ma_wb_dat_i), .m_wb_dat_o(eth_ma_wb_dat_o), .m_wb_cyc_o(eth_ma_wb_cyc_o),
|
.m_wb_dat_i(eth_ma_wb_dat_i), .m_wb_dat_o(eth_ma_wb_dat_o), .m_wb_cyc_o(eth_ma_wb_cyc_o),
|
.m_wb_stb_o(eth_ma_wb_stb_o), .m_wb_ack_i(eth_ma_wb_ack_i), .m_wb_err_i(eth_ma_wb_err_i),
|
.m_wb_stb_o(eth_ma_wb_stb_o), .m_wb_ack_i(eth_ma_wb_ack_i), .m_wb_err_i(eth_ma_wb_err_i),
|
|
|
|
`ifdef ETH_WISHBONE_B3
|
|
.m_wb_cti_o(eth_ma_wb_cti_o), .m_wb_bte_o(eth_ma_wb_bte_o),
|
|
`endif
|
|
|
//TX
|
//TX
|
.mtx_clk_pad_i(mtx_clk), .mtxd_pad_o(MTxD), .mtxen_pad_o(MTxEn), .mtxerr_pad_o(MTxErr),
|
.mtx_clk_pad_i(mtx_clk), .mtxd_pad_o(MTxD), .mtxen_pad_o(MTxEn), .mtxerr_pad_o(MTxErr),
|
|
|
//RX
|
//RX
|
.mrx_clk_pad_i(mrx_clk), .mrxd_pad_i(MRxD), .mrxdv_pad_i(MRxDV), .mrxerr_pad_i(MRxErr),
|
.mrx_clk_pad_i(mrx_clk), .mrxd_pad_i(MRxD), .mrxdv_pad_i(MRxDV), .mrxerr_pad_i(MRxErr),
|
| Line 289... |
Line 297... |
.ERR_O(eth_ma_wb_err_i),
|
.ERR_O(eth_ma_wb_err_i),
|
.RTY_O(), // NOT USED for now!
|
.RTY_O(), // NOT USED for now!
|
.SEL_I(eth_ma_wb_sel_o),
|
.SEL_I(eth_ma_wb_sel_o),
|
.STB_I(eth_ma_wb_stb_o),
|
.STB_I(eth_ma_wb_stb_o),
|
.WE_I (eth_ma_wb_we_o),
|
.WE_I (eth_ma_wb_we_o),
|
.CAB_I(1'b0) // inactive (1'b0)
|
.CAB_I(1'b0)
|
);
|
);
|
|
|
|
|
|
|
// Connecting WISHBONE Bus Monitors to ethernet master and slave interfaces
|
// Connecting WISHBONE Bus Monitors to ethernet master and slave interfaces
|
| Line 316... |
Line 324... |
.RTY_I(1'b0),
|
.RTY_I(1'b0),
|
.SEL_O(eth_sl_wb_sel_i),
|
.SEL_O(eth_sl_wb_sel_i),
|
.STB_O(eth_sl_wb_stb_i),
|
.STB_O(eth_sl_wb_stb_i),
|
.WE_O (eth_sl_wb_we_i),
|
.WE_O (eth_sl_wb_we_i),
|
.TAG_I({`WB_TAG_WIDTH{1'b0}}),
|
.TAG_I({`WB_TAG_WIDTH{1'b0}}),
|
.TAG_O(),
|
`ifdef ETH_WISHBONE_B3
|
|
.TAG_O({eth_ma_wb_cti_o, eth_ma_wb_bte_o}),
|
|
`else
|
|
.TAG_O(5'h0),
|
|
`endif
|
.CAB_O(1'b0),
|
.CAB_O(1'b0),
|
|
`ifdef ETH_WISHBONE_B3
|
|
.check_CTI (1'b1),
|
|
`else
|
|
.check_CTI (1'b0),
|
|
`endif
|
.log_file_desc (wb_s_mon_log_file_desc)
|
.log_file_desc (wb_s_mon_log_file_desc)
|
);
|
);
|
|
|
WB_BUS_MON wb_eth_master_bus_mon
|
WB_BUS_MON wb_eth_master_bus_mon
|
(
|
(
|
| Line 339... |
Line 356... |
.RTY_I(1'b0),
|
.RTY_I(1'b0),
|
.SEL_O(eth_ma_wb_sel_o),
|
.SEL_O(eth_ma_wb_sel_o),
|
.STB_O(eth_ma_wb_stb_o),
|
.STB_O(eth_ma_wb_stb_o),
|
.WE_O (eth_ma_wb_we_o),
|
.WE_O (eth_ma_wb_we_o),
|
.TAG_I({`WB_TAG_WIDTH{1'b0}}),
|
.TAG_I({`WB_TAG_WIDTH{1'b0}}),
|
.TAG_O(),
|
.TAG_O(5'h0),
|
.CAB_O(1'b0),
|
.CAB_O(1'b0),
|
|
.check_CTI(1'b0), // NO need
|
.log_file_desc(wb_m_mon_log_file_desc)
|
.log_file_desc(wb_m_mon_log_file_desc)
|
);
|
);
|
|
|
|
|
|
|
| Line 473... |
Line 491... |
// set DIFFERENT mrx_clk to mtx_clk!
|
// set DIFFERENT mrx_clk to mtx_clk!
|
// eth_phy.set_mrx_equal_mtx = 1'b0;
|
// eth_phy.set_mrx_equal_mtx = 1'b0;
|
|
|
// Call tests
|
// Call tests
|
// ----------
|
// ----------
|
// test_access_to_mac_reg(0, 0); // 0 - 3
|
test_access_to_mac_reg(0, 4); // 0 - 4
|
// test_mii(0, 17); // 0 - 17
|
test_mii(0, 17); // 0 - 17
|
test_note("PHY generates ideal Carrier sense and Collision signals for following tests");
|
test_note("PHY generates ideal Carrier sense and Collision signals for following tests");
|
eth_phy.carrier_sense_real_delay(0);
|
eth_phy.carrier_sense_real_delay(0);
|
test_mac_full_duplex_transmit(0, 21); // 0 - (21)
|
// test_mac_full_duplex_transmit(0, 21); // 0 - (21)
|
test_mac_full_duplex_receive(0, 13); // 0 - 13
|
|
test_mac_full_duplex_flow_control(0, 4); // 0 - 4
|
|
|
// test_mac_full_duplex_receive(2, 2); // 0 - 13
|
|
// test_mac_full_duplex_flow_control(0, 4); // 0 - 4
|
// 4 is executed, everything is OK
|
// 4 is executed, everything is OK
|
// test_mac_half_duplex_flow(0, 0);
|
// test_mac_half_duplex_flow(0, 0);
|
|
|
test_note("PHY generates 'real delayed' Carrier sense and Collision signals for following tests");
|
test_note("PHY generates 'real delayed' Carrier sense and Collision signals for following tests");
|
eth_phy.carrier_sense_real_delay(1);
|
eth_phy.carrier_sense_real_delay(1);
|
| Line 525... |
Line 545... |
integer i3;
|
integer i3;
|
integer fail;
|
integer fail;
|
integer test_num;
|
integer test_num;
|
reg [31:0] addr;
|
reg [31:0] addr;
|
reg [31:0] data;
|
reg [31:0] data;
|
|
reg [3:0] sel;
|
|
reg [3:0] rand_sel;
|
reg [31:0] data_max;
|
reg [31:0] data_max;
|
begin
|
begin
|
// ACCESS TO MAC REGISTERS TEST
|
// ACCESS TO MAC REGISTERS TEST
|
test_heading("ACCESS TO MAC REGISTERS TEST");
|
test_heading("ACCESS TO MAC REGISTERS TEST");
|
$display(" ");
|
$display(" ");
|
$display("ACCESS TO MAC REGISTERS TEST");
|
$display("ACCESS TO MAC REGISTERS TEST");
|
fail = 0;
|
fail = 0;
|
|
|
// reset MAC registers
|
// reset MAC registers
|
hard_reset;
|
hard_reset;
|
// reset MAC and MII LOGIC with soft reset
|
|
//reset_mac;
|
|
//reset_mii;
|
|
|
|
|
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// test_access_to_mac_reg: ////
|
//// test_access_to_mac_reg: ////
|
//// ////
|
//// ////
|
//// 0: Walking 1 with single cycles across MAC regs. ////
|
//// 0: Byte selects on 3 32-bit RW registers. ////
|
//// 1: Walking 1 with single cycles across MAC buffer descript. ////
|
//// 1: Walking 1 with single cycles across MAC regs. ////
|
//// 2: Test max reg. values and reg. values after writing ////
|
//// 2: Walking 1 with single cycles across MAC buffer descript. ////
|
|
//// 3: Test max reg. values and reg. values after writing ////
|
//// inverse reset values and hard reset of the MAC ////
|
//// inverse reset values and hard reset of the MAC ////
|
//// 3: Test buffer desc. RAM preserving values after hard reset ////
|
//// 4: Test buffer desc. RAM preserving values after hard reset ////
|
//// of the MAC and resetting the logic ////
|
//// of the MAC and resetting the logic ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
for (test_num = start_task; test_num <= end_task; test_num = test_num + 1)
|
for (test_num = start_task; test_num <= end_task; test_num = test_num + 1)
|
begin
|
begin
|
|
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Walking 1 with single cycles across MAC regs. ////
|
//// Byte selects on 4 32-bit RW registers. ////
|
//// ////
|
//// ////
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
if (test_num == 0) // Walking 1 with single cycles across MAC regs.
|
if (test_num == 0) // Walking 1 with single cycles across MAC regs.
|
begin
|
begin
|
// TEST 0: 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )
|
// TEST 0: BYTE SELECTS ON 3 32-BIT READ-WRITE REGISTERS ( VARIOUS BUS DELAYS )
|
test_name = "TEST 0: 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )";
|
test_name = "TEST 0: BYTE SELECTS ON 3 32-BIT READ-WRITE REGISTERS ( VARIOUS BUS DELAYS )";
|
`TIME; $display(" TEST 0: 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )");
|
`TIME; $display(" TEST 0: BYTE SELECTS ON 3 32-BIT READ-WRITE REGISTERS ( VARIOUS BUS DELAYS )");
|
|
|
data = 0;
|
data = 0;
|
for (i = 0; i <= 4; i = i + 1) // for initial wait cycles on WB bus
|
rand_sel = 0;
|
|
sel = 0;
|
|
for (i = 1; i <= 3; i = i + 1) // num of active byte selects at each register
|
begin
|
begin
|
wbm_init_waits = i;
|
wbm_init_waits = 0;
|
wbm_subseq_waits = {$random} % 5; // it is not important for single accesses
|
wbm_subseq_waits = {$random} % 5; // it is not important for single accesses
|
for (i_addr = 0; i_addr <= 32'h4C; i_addr = i_addr + 4) // register address
|
case (i)
|
|
1: i_addr = `ETH_MAC_ADDR0;
|
|
2: i_addr = `ETH_HASH_ADDR0;
|
|
default: i_addr = `ETH_HASH_ADDR1;
|
|
endcase
|
|
addr = `ETH_BASE + i_addr;
|
|
sel = 4'hF;
|
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if (tmp_data !== 32'h0)
|
|
begin
|
|
fail = fail + 1;
|
|
test_fail_num("Register default value is not ZERO", i_addr);
|
|
`TIME;
|
|
$display("Register default value is not ZERO - addr %h, tmp_data %h", addr, tmp_data);
|
|
end
|
|
for (i1 = 0; i1 <= 3; i1 = i1 + 1) // position of first active byte select
|
begin
|
begin
|
|
case ({i, i1})
|
|
10: sel = 4'b0001; // data = 32'hFFFF_FF00;
|
|
11: sel = 4'b0010; // data = 32'hFFFF_00FF;
|
|
12: sel = 4'b0100; // data = 32'hFF00_FFFF;
|
|
13: sel = 4'b1000; // data = 32'h00FF_FFFF;
|
|
20: sel = 4'b0011; // data = 32'hFFFF_0000;
|
|
21: sel = 4'b0110; // data = 32'hFF00_00FF;
|
|
22: sel = 4'b1100; // data = 32'h0000_FFFF;
|
|
23: sel = 4'b1001; // data = 32'h00FF_FF00;
|
|
30: sel = 4'b0111; // data = 32'hFF00_0000;
|
|
31: sel = 4'b1110; // data = 32'h0000_00FF;
|
|
32: sel = 4'b1101; // data = 32'h0000_FF00;
|
|
default: sel = 4'b1011; // data = 32'h00FF_0000;
|
|
endcase
|
|
// set value to 32'hFFFF_FFFF
|
|
data = 32'hFFFF_FFFF;
|
|
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
wait (wbm_working == 0);
|
|
wbm_read(addr, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if (tmp_data !== data)
|
|
begin
|
|
fail = fail + 1;
|
|
test_fail_num("Register could not be written to FFFF_FFFF", i_addr);
|
|
`TIME;
|
|
$display("Register could not be written to FFFF_FFFF - addr %h, tmp_data %h", addr, tmp_data);
|
|
end
|
|
// write appropriate byte(s) to 0
|
|
data = 32'h0;
|
|
wbm_write(addr, data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
|
wait (wbm_working == 0);
|
|
if (i1[0])
|
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
|
else
|
|
wbm_read(addr, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
data = {({8{~sel[3]}}), ({8{~sel[2]}}), ({8{~sel[1]}}), ({8{~sel[0]}})};
|
|
if (tmp_data !== data)
|
|
begin
|
|
fail = fail + 1;
|
|
test_fail_num("Wrong data read out form register", i_addr);
|
|
`TIME;
|
|
$display("Wrong data read out from register - addr %h, data %h, tmp_data %h, sel %b",
|
|
addr, data, tmp_data, sel);
|
|
end
|
|
end
|
|
end
|
|
if(fail == 0)
|
|
test_ok;
|
|
else
|
|
fail = 0; // Errors were reported previously
|
|
end
|
|
|
|
|
|
////////////////////////////////////////////////////////////////////
|
|
//// ////
|
|
//// Walking 1 with single cycles across MAC regs. ////
|
|
//// ////
|
|
////////////////////////////////////////////////////////////////////
|
|
if (test_num == 1) // Walking 1 with single cycles across MAC regs.
|
|
begin
|
|
// TEST 1: 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )
|
|
test_name = "TEST 1: 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )";
|
|
`TIME; $display(" TEST 1: 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )");
|
|
|
|
data = 0;
|
|
rand_sel = 0;
|
|
sel = 0;
|
|
for (i_addr = 0; i_addr <= {22'h0, `ETH_TX_CTRL_ADR, 2'h0}; i_addr = i_addr + 4) // register address
|
|
begin
|
|
if (i_addr[6:4] < 5)
|
|
wbm_init_waits = i_addr[6:4];
|
|
else
|
|
wbm_init_waits = 4;
|
|
wbm_subseq_waits = {$random} % 5; // it is not important for single accesses
|
addr = `ETH_BASE + i_addr;
|
addr = `ETH_BASE + i_addr;
|
// set ranges of R/W bits
|
// set ranges of R/W bits
|
case (addr)
|
case (addr)
|
`ETH_MODER:
|
`ETH_MODER:
|
begin
|
begin
|
| Line 649... |
Line 759... |
bit_end_2 = 32; // not used
|
bit_end_2 = 32; // not used
|
end
|
end
|
`ETH_MIIMODER:
|
`ETH_MIIMODER:
|
begin
|
begin
|
bit_start_1 = 0;
|
bit_start_1 = 0;
|
bit_end_1 = 9;
|
bit_end_1 = 8;
|
bit_start_2 = 32; // not used
|
bit_start_2 = 32; // not used
|
bit_end_2 = 32; // not used
|
bit_end_2 = 32; // not used
|
end
|
end
|
`ETH_MIICOMMAND: // "WRITEONLY" - tested within MIIM test - 3 LSBits are not written here!!!
|
`ETH_MIICOMMAND: // "WRITEONLY" - tested within MIIM test - 3 LSBits are not written here!!!
|
begin
|
begin
|
| Line 709... |
Line 819... |
bit_start_1 = 0;
|
bit_start_1 = 0;
|
bit_end_1 = 31;
|
bit_end_1 = 31;
|
bit_start_2 = 32; // not used
|
bit_start_2 = 32; // not used
|
bit_end_2 = 32; // not used
|
bit_end_2 = 32; // not used
|
end
|
end
|
default: // `ETH_HASH_ADDR1:
|
`ETH_HASH_ADDR1:
|
begin
|
begin
|
bit_start_1 = 0;
|
bit_start_1 = 0;
|
bit_end_1 = 31;
|
bit_end_1 = 31;
|
bit_start_2 = 32; // not used
|
bit_start_2 = 32; // not used
|
bit_end_2 = 32; // not used
|
bit_end_2 = 32; // not used
|
end
|
end
|
|
default: // `ETH_TX_CTRL_ADR:
|
|
begin
|
|
bit_start_1 = 0;
|
|
bit_end_1 = 16;
|
|
bit_start_2 = 32; // not used
|
|
bit_end_2 = 32; // not used
|
|
end
|
endcase
|
endcase
|
|
|
for (i_data = 0; i_data <= 31; i_data = i_data + 1) // the position of walking one
|
for (i_data = 0; i_data <= 31; i_data = i_data + 1) // the position of walking one
|
begin
|
begin
|
data = 1'b1 << i_data;
|
data = 1'b1 << i_data;
|
if ( (addr == `ETH_MIICOMMAND) && (i_data <= 2) ) // DO NOT WRITE to 3 LSBits of MIICOMMAND !!!
|
if ( (addr == `ETH_MIICOMMAND)/* && (i_data <= 2)*/ ) // DO NOT WRITE to 3 LSBits of MIICOMMAND !!!
|
;
|
;
|
else
|
else
|
begin
|
begin
|
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
rand_sel[2:0] = {$random} % 8;
|
|
if ((i_data >= 0) && (i_data < 8))
|
|
sel = {rand_sel[2:0], 1'b1};
|
|
else if ((i_data >= 8) && (i_data < 16))
|
|
sel = {rand_sel[2:1], 1'b1, rand_sel[0]};
|
|
else if ((i_data >= 16) && (i_data < 24))
|
|
sel = {rand_sel[2], 1'b1, rand_sel[1:0]};
|
|
else // if ((i_data >= 24) && (i_data < 32))
|
|
sel = {1'b1, rand_sel[2:0]};
|
|
wbm_write(addr, data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_read(addr, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
if ( ((i_data >= bit_start_1) && (i_data <= bit_end_1)) ||
|
if ( ((i_data >= bit_start_1) && (i_data <= bit_end_1)) ||
|
((i_data >= bit_start_2) && (i_data <= bit_end_2)) ) // data should be equal to tmp_data
|
((i_data >= bit_start_2) && (i_data <= bit_end_2)) ) // data should be equal to tmp_data
|
begin
|
begin
|
if (tmp_data !== data)
|
if ( ((tmp_data[31:24] !== data[31:24]) && sel[3]) || ((tmp_data[23:16] !== data[23:16]) && sel[2]) ||
|
|
((tmp_data[15: 8] !== data[15: 8]) && sel[1]) || ((tmp_data[ 7: 0] !== data[ 7: 0]) && sel[0]) )
|
begin
|
begin
|
fail = fail + 1;
|
fail = fail + 1;
|
test_fail("RW bit of the MAC register was not written or not read");
|
test_fail_num("RW bit of the MAC register was not written or not read", i_addr);
|
`TIME;
|
`TIME;
|
$display("wbm_init_waits %d, addr %h, data %h, tmp_data %h",
|
$display("Wrong RW bit - wbm_init_waits %d, addr %h, data %h, tmp_data %h, sel %b",
|
wbm_init_waits, addr, data, tmp_data);
|
wbm_init_waits, addr, data, tmp_data, sel);
|
end
|
end
|
end
|
end
|
else // data should not be equal to tmp_data
|
else // data should not be equal to tmp_data
|
begin
|
begin
|
if (tmp_data === data)
|
if ( ((tmp_data[31:24] === data[31:24]) && sel[3]) && ((tmp_data[23:16] === data[23:16]) && sel[2]) &&
|
|
((tmp_data[15: 8] === data[15: 8]) && sel[1]) && ((tmp_data[ 7: 0] === data[ 7: 0]) && sel[0]) )
|
begin
|
begin
|
fail = fail + 1;
|
fail = fail + 1;
|
test_fail("NON RW bit of the MAC register was written, but it shouldn't be");
|
test_fail_num("NON RW bit of the MAC register was written, but it shouldn't be", i_addr);
|
`TIME;
|
`TIME;
|
$display("wbm_init_waits %d, addr %h, data %h, tmp_data %h",
|
$display("Wrong NON RW bit - wbm_init_waits %d, addr %h, data %h, tmp_data %h, sel %b",
|
wbm_init_waits, addr, data, tmp_data);
|
wbm_init_waits, addr, data, tmp_data, sel);
|
end
|
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
// INTERMEDIATE DISPLAYS (The only one)
|
// INTERMEDIATE DISPLAYS (The only one)
|
$display(" ->buffer descriptors tested with 0, 1, 2, 3 and 4 bus delay cycles");
|
$display(" ->registers tested with 0, 1, 2, 3 and 4 bus delay cycles");
|
if(fail == 0)
|
if(fail == 0)
|
test_ok;
|
test_ok;
|
else
|
else
|
fail = 0; // Errors were reported previously
|
fail = 0; // Errors were reported previously
|
end
|
end
|
| Line 769... |
Line 896... |
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Walking 1 with single cycles across MAC buffer descript. ////
|
//// Walking 1 with single cycles across MAC buffer descript. ////
|
//// ////
|
//// ////
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
if (test_num == 1) // Start Walking 1 with single cycles across MAC buffer descript.
|
if (test_num == 2) // Start Walking 1 with single cycles across MAC buffer descript.
|
begin
|
begin
|
// TEST 1: 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC BUFFER DESC. ( VARIOUS BUS DELAYS )
|
// TEST 2: 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC BUFFER DESC. ( VARIOUS BUS DELAYS )
|
test_name = "TEST 1: 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC BUFFER DESC. ( VARIOUS BUS DELAYS )";
|
test_name = "TEST 2: 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC BUFFER DESC. ( VARIOUS BUS DELAYS )";
|
`TIME; $display(" TEST 1: 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC BUFFER DESC. ( VARIOUS BUS DELAYS )");
|
`TIME; $display(" TEST 2: 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC BUFFER DESC. ( VARIOUS BUS DELAYS )");
|
|
|
data = 0;
|
data = 0;
|
|
rand_sel = 0;
|
|
sel = 0;
|
// set TX and RX buffer descriptors
|
// set TX and RX buffer descriptors
|
tx_bd_num = 32'h40;
|
tx_bd_num = 32'h40;
|
wbm_write(`ETH_TX_BD_NUM, tx_bd_num, 4'hF, 1, 0, 0);
|
wbm_write(`ETH_TX_BD_NUM, tx_bd_num, 4'hF, 1, 0, 0);
|
for (i = 0; i <= 4; i = i + 1) // for initial wait cycles on WB bus
|
|
begin
|
|
wbm_init_waits = i;
|
|
wbm_subseq_waits = {$random} % 5; // it is not important for single accesses
|
|
for (i_addr = 32'h400; i_addr <= 32'h7FC; i_addr = i_addr + 4) // buffer descriptor address
|
for (i_addr = 32'h400; i_addr <= 32'h7FC; i_addr = i_addr + 4) // buffer descriptor address
|
begin
|
begin
|
|
if (i_addr[11:8] < 8)
|
|
wbm_init_waits = i_addr[10:8] - 3'h4;
|
|
else
|
|
wbm_init_waits = 3;
|
|
wbm_subseq_waits = {$random} % 5; // it is not important for single accesses
|
addr = `ETH_BASE + i_addr;
|
addr = `ETH_BASE + i_addr;
|
if (i_addr < (32'h400 + (tx_bd_num << 3))) // TX buffer descriptors
|
if (i_addr < (32'h400 + (tx_bd_num << 3))) // TX buffer descriptors
|
begin
|
begin
|
// set ranges of R/W bits
|
// set ranges of R/W bits
|
case (addr[3])
|
case (addr[3])
|
| Line 834... |
Line 964... |
data = 1'b1 << i_data;
|
data = 1'b1 << i_data;
|
if ( (addr[3] == 0) && (i_data == 15) ) // DO NOT WRITE to this bit !!!
|
if ( (addr[3] == 0) && (i_data == 15) ) // DO NOT WRITE to this bit !!!
|
;
|
;
|
else
|
else
|
begin
|
begin
|
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
rand_sel[2:0] = {$random} % 8;
|
wbm_read(addr, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
if ((i_data >= 0) && (i_data < 8))
|
|
sel = {rand_sel[2:0], 1'b1};
|
|
else if ((i_data >= 8) && (i_data < 16))
|
|
sel = {rand_sel[2:1], 1'b1, rand_sel[0]};
|
|
else if ((i_data >= 16) && (i_data < 24))
|
|
sel = {rand_sel[2], 1'b1, rand_sel[1:0]};
|
|
else // if ((i_data >= 24) && (i_data < 32))
|
|
sel = {1'b1, rand_sel[2:0]};
|
|
wbm_write(addr, data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
if ( ((i_data >= bit_start_1) && (i_data <= bit_end_1)) ||
|
if ( ((i_data >= bit_start_1) && (i_data <= bit_end_1)) ||
|
((i_data >= bit_start_2) && (i_data <= bit_end_2)) ) // data should be equal to tmp_data
|
((i_data >= bit_start_2) && (i_data <= bit_end_2)) ) // data should be equal to tmp_data
|
begin
|
begin
|
if (tmp_data !== data)
|
if ( ((tmp_data[31:24] !== data[31:24]) && sel[3]) || ((tmp_data[23:16] !== data[23:16]) && sel[2]) ||
|
|
((tmp_data[15: 8] !== data[15: 8]) && sel[1]) || ((tmp_data[ 7: 0] !== data[ 7: 0]) && sel[0]) )
|
begin
|
begin
|
fail = fail + 1;
|
fail = fail + 1;
|
test_fail("RW bit of the MAC buffer descriptors was not written or not read");
|
test_fail("RW bit of the MAC buffer descriptors was not written or not read");
|
`TIME;
|
`TIME;
|
$display("wbm_init_waits %d, addr %h, data %h, tmp_data %h",
|
$display("Wrong RW bit - wbm_init_waits %d, addr %h, data %h, tmp_data %h, sel %b",
|
wbm_init_waits, addr, data, tmp_data);
|
wbm_init_waits, addr, data, tmp_data, sel);
|
end
|
end
|
end
|
end
|
else // data should not be equal to tmp_data
|
else // data should not be equal to tmp_data
|
begin
|
begin
|
if (tmp_data === data)
|
if ( ((tmp_data[31:24] === data[31:24]) && sel[3]) && ((tmp_data[23:16] === data[23:16]) && sel[2]) &&
|
|
((tmp_data[15: 8] === data[15: 8]) && sel[1]) && ((tmp_data[ 7: 0] === data[ 7: 0]) && sel[0]) )
|
begin
|
begin
|
fail = fail + 1;
|
fail = fail + 1;
|
test_fail("NON RW bit of the MAC buffer descriptors was written, but it shouldn't be");
|
test_fail("NON RW bit of the MAC buffer descriptors was written, but it shouldn't be");
|
`TIME;
|
`TIME;
|
$display("wbm_init_waits %d, addr %h, data %h, tmp_data %h",
|
$display("Wrong NON RW bit - wbm_init_waits %d, addr %h, data %h, tmp_data %h, sel %b",
|
wbm_init_waits, addr, data, tmp_data);
|
wbm_init_waits, addr, data, tmp_data, sel);
|
end
|
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
// INTERMEDIATE DISPLAYS
|
// INTERMEDIATE DISPLAYS
|
case (i)
|
if (i_addr[11:0] == 12'h500)
|
0: $display(" ->buffer descriptors tested with 0 bus delay");
|
$display(" ->buffer descriptors tested with 0 bus delay");
|
1: $display(" ->buffer descriptors tested with 1 bus delay cycle");
|
else if (i_addr[11:0] == 12'h600)
|
2: $display(" ->buffer descriptors tested with 2 bus delay cycles");
|
$display(" ->buffer descriptors tested with 1 bus delay cycle");
|
3: $display(" ->buffer descriptors tested with 3 bus delay cycles");
|
else if (i_addr[11:0] == 12'h700)
|
default: $display(" ->buffer descriptors tested with 4 bus delay cycles");
|
$display(" ->buffer descriptors tested with 2 bus delay cycles");
|
endcase
|
|
end
|
end
|
|
$display(" ->buffer descriptors tested with 3 bus delay cycles");
|
if(fail == 0)
|
if(fail == 0)
|
test_ok;
|
test_ok;
|
else
|
else
|
fail = 0;
|
fail = 0;
|
end
|
end
|
| Line 884... |
Line 1024... |
//// ////
|
//// ////
|
//// Test max reg. values and reg. values after writing ////
|
//// Test max reg. values and reg. values after writing ////
|
//// inverse reset values and hard reset of the MAC ////
|
//// inverse reset values and hard reset of the MAC ////
|
//// ////
|
//// ////
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
if (test_num == 2) // Start this task
|
if (test_num == 3) // Start this task
|
begin
|
begin
|
// TEST 2: MAX REG. VALUES AND REG. VALUES AFTER WRITING INVERSE RESET VALUES AND HARD RESET OF THE MAC
|
// TEST 3: MAX REG. VALUES AND REG. VALUES AFTER WRITING INVERSE RESET VALUES AND HARD RESET OF THE MAC
|
test_name =
|
test_name =
|
"TEST 2: MAX REG. VALUES AND REG. VALUES AFTER WRITING INVERSE RESET VALUES AND HARD RESET OF THE MAC";
|
"TEST 3: MAX REG. VALUES AND REG. VALUES AFTER WRITING INVERSE RESET VALUES AND HARD RESET OF THE MAC";
|
`TIME; $display(
|
`TIME; $display(
|
" TEST 2: MAX REG. VALUES AND REG. VALUES AFTER WRITING INVERSE RESET VALUES AND HARD RESET OF THE MAC");
|
" TEST 3: MAX REG. VALUES AND REG. VALUES AFTER WRITING INVERSE RESET VALUES AND HARD RESET OF THE MAC");
|
|
|
// reset MAC registers
|
// reset MAC registers
|
hard_reset;
|
hard_reset;
|
for (i = 0; i <= 4; i = i + 1) // 0, 2 - WRITE; 1, 3, 4 - READ
|
for (i = 0; i <= 4; i = i + 1) // 0, 2 - WRITE; 1, 3, 4 - READ
|
begin
|
begin
|
for (i_addr = 0; i_addr <= 32'h4C; i_addr = i_addr + 4) // register address
|
for (i_addr = 0; i_addr <= {22'h0, `ETH_TX_CTRL_ADR, 2'h0}; i_addr = i_addr + 4) // register address
|
begin
|
begin
|
addr = `ETH_BASE + i_addr;
|
addr = `ETH_BASE + i_addr;
|
// set ranges of R/W bits
|
// set ranges of R/W bits
|
case (addr)
|
case (addr)
|
`ETH_MODER:
|
`ETH_MODER:
|
begin
|
begin
|
data = 32'h0000_A800;
|
data = 32'h0000_A000; // bit 11 not used any more
|
data_max = 32'h0001_FFFF;
|
data_max = 32'h0001_FFFF;
|
end
|
end
|
`ETH_INT: // READONLY - tested within INT test
|
`ETH_INT: // READONLY - tested within INT test
|
begin
|
begin
|
data = 32'h0000_0000;
|
data = 32'h0000_0000;
|
| Line 954... |
Line 1094... |
data_max = 32'h0000_0007;
|
data_max = 32'h0000_0007;
|
end
|
end
|
`ETH_MIIMODER:
|
`ETH_MIIMODER:
|
begin
|
begin
|
data = 32'h0000_0064;
|
data = 32'h0000_0064;
|
data_max = 32'h0000_03FF;
|
data_max = 32'h0000_01FF;
|
end
|
end
|
`ETH_MIICOMMAND: // "WRITEONLY" - tested within MIIM test - 3 LSBits are not written here!!!
|
`ETH_MIICOMMAND: // "WRITEONLY" - tested within MIIM test - 3 LSBits are not written here!!!
|
begin
|
begin
|
data = 32'h0000_0000;
|
data = 32'h0000_0000;
|
data_max = 32'h0000_0007;
|
data_max = 32'h0000_0000;
|
end
|
end
|
`ETH_MIIADDRESS:
|
`ETH_MIIADDRESS:
|
begin
|
begin
|
data = 32'h0000_0000;
|
data = 32'h0000_0000;
|
data_max = 32'h0000_1F1F;
|
data_max = 32'h0000_1F1F;
|
| Line 996... |
Line 1136... |
`ETH_HASH_ADDR0:
|
`ETH_HASH_ADDR0:
|
begin
|
begin
|
data = 32'h0000_0000;
|
data = 32'h0000_0000;
|
data_max = 32'hFFFF_FFFF;
|
data_max = 32'hFFFF_FFFF;
|
end
|
end
|
default: // `ETH_HASH_ADDR1:
|
`ETH_HASH_ADDR1:
|
begin
|
begin
|
data = 32'h0000_0000;
|
data = 32'h0000_0000;
|
data_max = 32'hFFFF_FFFF;
|
data_max = 32'hFFFF_FFFF;
|
end
|
end
|
|
default: // `ETH_TX_CTRL_ADR:
|
|
begin
|
|
data = 32'h0000_0000;
|
|
data_max = 32'h0000_FFFF;
|
|
end
|
endcase
|
endcase
|
|
|
wbm_init_waits = {$random} % 3;
|
wbm_init_waits = {$random} % 3;
|
wbm_subseq_waits = {$random} % 5; // it is not important for single accesses
|
wbm_subseq_waits = {$random} % 5; // it is not important for single accesses
|
if (i == 0)
|
if (i == 0)
|
begin
|
begin
|
|
if (addr == `ETH_MIICOMMAND) // DO NOT WRITE to 3 LSBits of MIICOMMAND !!!
|
|
;
|
|
else
|
wbm_write(addr, ~data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_write(addr, ~data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
end
|
end
|
else if (i == 2)
|
else if (i == 2)
|
begin
|
begin
|
|
if (addr == `ETH_MIICOMMAND) // DO NOT WRITE to 3 LSBits of MIICOMMAND !!!
|
|
;
|
|
else
|
wbm_write(addr, 32'hFFFFFFFF, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_write(addr, 32'hFFFFFFFF, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
end
|
end
|
else if ((i == 1) || (i == 4))
|
else if ((i == 1) || (i == 4))
|
begin
|
begin
|
wbm_read(addr, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
| Line 1096... |
Line 1247... |
//// ////
|
//// ////
|
//// Test buffer desc. ram preserving values after hard reset ////
|
//// Test buffer desc. ram preserving values after hard reset ////
|
//// of the mac and reseting the logic ////
|
//// of the mac and reseting the logic ////
|
//// ////
|
//// ////
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
if (test_num == 3) // Start this task
|
if (test_num == 4) // Start this task
|
begin
|
begin
|
// TEST 3: BUFFER DESC. RAM PRESERVING VALUES AFTER HARD RESET OF THE MAC AND RESETING THE LOGIC
|
// TEST 4: BUFFER DESC. RAM PRESERVING VALUES AFTER HARD RESET OF THE MAC AND RESETING THE LOGIC
|
test_name = "TEST 3: BUFFER DESC. RAM PRESERVING VALUES AFTER HARD RESET OF THE MAC AND RESETING THE LOGIC";
|
test_name = "TEST 4: BUFFER DESC. RAM PRESERVING VALUES AFTER HARD RESET OF THE MAC AND RESETING THE LOGIC";
|
`TIME;
|
`TIME;
|
$display(" TEST 3: BUFFER DESC. RAM PRESERVING VALUES AFTER HARD RESET OF THE MAC AND RESETING THE LOGIC");
|
$display(" TEST 4: BUFFER DESC. RAM PRESERVING VALUES AFTER HARD RESET OF THE MAC AND RESETING THE LOGIC");
|
|
|
// reset MAC registers
|
// reset MAC registers
|
hard_reset;
|
hard_reset;
|
// reset LOGIC with soft reset
|
|
// reset_mac;
|
|
// reset_mii;
|
|
for (i = 0; i <= 3; i = i + 1) // 0, 2 - WRITE; 1, 3 - READ
|
for (i = 0; i <= 3; i = i + 1) // 0, 2 - WRITE; 1, 3 - READ
|
begin
|
begin
|
for (i_addr = 32'h400; i_addr <= 32'h7FC; i_addr = i_addr + 4) // buffer descriptor address
|
for (i_addr = 32'h400; i_addr <= 32'h7FC; i_addr = i_addr + 4) // buffer descriptor address
|
begin
|
begin
|
addr = `ETH_BASE + i_addr;
|
addr = `ETH_BASE + i_addr;
|
| Line 1142... |
Line 1290... |
end
|
end
|
if ((i == 0) || (i == 2))
|
if ((i == 0) || (i == 2))
|
begin
|
begin
|
// reset MAC registers
|
// reset MAC registers
|
hard_reset;
|
hard_reset;
|
// reset LOGIC with soft reset
|
|
// reset_mac;
|
|
// reset_mii;
|
|
end
|
end
|
end
|
end
|
if(fail == 0)
|
if(fail == 0)
|
test_ok;
|
test_ok;
|
else
|
else
|
fail = 0;
|
fail = 0;
|
end
|
end
|
|
|
|
|
if (test_num == 4) // Start this task
|
if (test_num == 5) // Start this task
|
begin
|
begin
|
/* // TEST 4: 'WALKING ONE' WITH BURST CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )
|
/* // TEST 5: 'WALKING ONE' WITH BURST CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )
|
test_name = "TEST 4: 'WALKING ONE' WITH BURST CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )";
|
test_name = "TEST 5: 'WALKING ONE' WITH BURST CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )";
|
`TIME; $display(" TEST 4: 'WALKING ONE' WITH BURST CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )");
|
`TIME; $display(" TEST 5: 'WALKING ONE' WITH BURST CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )");
|
|
|
data = 0;
|
data = 0;
|
burst_data = 0;
|
burst_data = 0;
|
burst_tmp_data = 0;
|
burst_tmp_data = 0;
|
i_length = 10; // two bursts for length 20
|
i_length = 10; // two bursts for length 20
|
| Line 1431... |
Line 1576... |
$display("MIIM MODULE TEST");
|
$display("MIIM MODULE TEST");
|
fail = 0;
|
fail = 0;
|
|
|
// reset MAC registers
|
// reset MAC registers
|
hard_reset;
|
hard_reset;
|
// reset MAC and MII LOGIC with soft reset
|
|
//reset_mac;
|
|
//reset_mii;
|
|
|
|
|
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// test_mii: ////
|
//// test_mii: ////
|
| Line 1926... |
Line 2068... |
phy_addr = 5'h2; // wrong PHY address
|
phy_addr = 5'h2; // wrong PHY address
|
// read request
|
// read request
|
#Tp mii_read_req(phy_addr, reg_addr);
|
#Tp mii_read_req(phy_addr, reg_addr);
|
check_mii_busy; // wait for read to finish
|
check_mii_busy; // wait for read to finish
|
// read data
|
// read data
|
$display(" => Two errors will be displayed from WB Bus Monitor, because correct HIGH Z data was read");
|
$display(" => Two error lines will be displayed from WB Bus Monitor, because correct HIGH Z data was read");
|
wbm_read(`ETH_MIIRX_DATA, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(`ETH_MIIRX_DATA, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
if (tmp_data !== 16'hzzzz)
|
if (tmp_data !== 16'hzzzz)
|
begin
|
begin
|
test_fail("Data was read from PHY register with wrong PHY address - control register");
|
test_fail("Data was read from PHY register with wrong PHY address - control register");
|
fail = fail + 1;
|
fail = fail + 1;
|
| Line 3017... |
Line 3159... |
begin
|
begin
|
#Tp eth_phy.preamble_suppresed(i);
|
#Tp eth_phy.preamble_suppresed(i);
|
// MII mode register
|
// MII mode register
|
wbm_write(`ETH_MIIMODER, (`ETH_MIIMODER_NOPRE & {23'h0, i, 8'h0}) | (`ETH_MIIMODER_CLKDIV & clk_div),
|
wbm_write(`ETH_MIIMODER, (`ETH_MIIMODER_NOPRE & {23'h0, i, 8'h0}) | (`ETH_MIIMODER_CLKDIV & clk_div),
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
if (i)
|
|
begin
|
|
// change saved data when preamble is suppressed
|
|
#Tp tmp_data = tmp_data | 16'h0040; // put bit 6 to ONE
|
|
end
|
|
|
|
// scan request
|
// scan request
|
#Tp mii_scan_req(phy_addr, reg_addr);
|
#Tp mii_scan_req(phy_addr, reg_addr);
|
check_mii_scan_valid; // wait for scan to make first data valid
|
check_mii_scan_valid; // wait for scan to make first data valid
|
|
|
fork
|
fork
|
| Line 3262... |
Line 3398... |
begin
|
begin
|
#Tp eth_phy.preamble_suppresed(i2);
|
#Tp eth_phy.preamble_suppresed(i2);
|
// MII mode register
|
// MII mode register
|
#Tp wbm_write(`ETH_MIIMODER, (`ETH_MIIMODER_NOPRE & {23'h0, i2, 8'h0}), 4'hF, 1, wbm_init_waits,
|
#Tp wbm_write(`ETH_MIIMODER, (`ETH_MIIMODER_NOPRE & {23'h0, i2, 8'h0}), 4'hF, 1, wbm_init_waits,
|
wbm_subseq_waits);
|
wbm_subseq_waits);
|
if (i2)
|
|
begin
|
|
// change saved data when preamble is suppressed
|
|
#Tp tmp_data = tmp_data | 16'h0040; // put bit 6 to ONE
|
|
end
|
|
|
|
i = 0;
|
i = 0;
|
while (i < 80) // delay for sliding of LinkFail bit
|
while (i < 80) // delay for sliding of LinkFail bit
|
begin
|
begin
|
// first there are two scans
|
// first there are two scans
|
#Tp cnt = 0;
|
#Tp cnt = 0;
|
| Line 8003... |
Line 8133... |
|
|
max_tmp = 0;
|
max_tmp = 0;
|
min_tmp = 0;
|
min_tmp = 0;
|
num_of_frames = 0;
|
num_of_frames = 0;
|
num_of_bd = 0;
|
num_of_bd = 0;
|
|
tx_bd_num = 0;
|
// set 13 TX buffer descriptors - must be set before TX enable
|
// set 13 TX buffer descriptors - must be set before TX enable
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_write(`ETH_TX_BD_NUM, 32'hD, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_write(`ETH_TX_BD_NUM, 32'hD, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
// enable TX, set full-duplex mode, NO padding and CRC appending
|
// enable TX, set full-duplex mode, NO padding and CRC appending
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
| Line 8051... |
Line 8182... |
set_tx_bd(2, 2, i_length+2, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
|
set_tx_bd(2, 2, i_length+2, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
|
set_tx_bd_wrap(2);
|
set_tx_bd_wrap(2);
|
set_tx_bd_ready(0, 0);
|
set_tx_bd_ready(0, 0);
|
end
|
end
|
else if (num_of_bd == 1)
|
else if (num_of_bd == 1)
|
|
begin
|
set_tx_bd_ready(1, 1);
|
set_tx_bd_ready(1, 1);
|
|
tx_bd_num = 1;
|
|
end
|
else if (num_of_bd == 2)
|
else if (num_of_bd == 2)
|
|
begin
|
set_tx_bd_ready(2, 2);
|
set_tx_bd_ready(2, 2);
|
|
tx_bd_num = 2;
|
|
end
|
else if (num_of_bd == 3)
|
else if (num_of_bd == 3)
|
begin
|
begin
|
set_tx_bd(0, 0, 100, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
|
set_tx_bd(0, 0, 100, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
|
set_tx_bd_wrap(2);
|
set_tx_bd_wrap(2);
|
set_tx_bd_ready(0, 0);
|
set_tx_bd_ready(0, 0);
|
i_length = 96;
|
i_length = 100;
|
|
tx_bd_num = 0;
|
end
|
end
|
|
|
|
|
// CHECK END OF TRANSMITION
|
// CHECK END OF TRANSMITION
|
check_tx_bd(num_of_bd, data);
|
check_tx_bd(tx_bd_num, data);
|
wait (MTxEn === 1'b1); // start transmit
|
wait (MTxEn === 1'b1); // start transmit
|
check_tx_bd(num_of_bd, data);
|
check_tx_bd(tx_bd_num, data);
|
if (data[15] !== 1)
|
if (data[15] !== 1)
|
begin
|
begin
|
test_fail("Wrong buffer descriptor's ready bit read out from MAC");
|
test_fail("Wrong buffer descriptor's ready bit read out from MAC");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
wait (MTxEn === 1'b0); // end transmit
|
wait (MTxEn === 1'b0); // end transmit
|
while (data[15] === 1)
|
while (data[15] === 1)
|
begin
|
begin
|
check_tx_bd(num_of_bd, data);
|
check_tx_bd(tx_bd_num, data);
|
@(posedge wb_clk);
|
@(posedge wb_clk);
|
end
|
end
|
repeat (1) @(posedge wb_clk);
|
repeat (1) @(posedge wb_clk);
|
// check length of a PACKET
|
// check length of a PACKET
|
tmp_len = eth_phy.tx_len;
|
tmp_len = eth_phy.tx_len;
|
#1;
|
#1;
|
|
if ((i_length + 4) <= max_tmp)
|
|
begin
|
if (tmp_len != (i_length + 4))
|
if (tmp_len != (i_length + 4))
|
begin
|
begin
|
test_fail("Wrong length of the packet out from MAC");
|
test_fail("Wrong length of the packet out from MAC");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
|
end
|
|
else
|
|
begin
|
|
if (tmp_len != (i_length + 4 - 1))
|
|
begin
|
|
test_fail("Wrong length of the packet out from MAC");
|
|
fail = fail + 1;
|
|
end
|
|
end
|
|
|
// check transmitted TX packet data
|
// check transmitted TX packet data
|
if ((i_length + 4) == 100)
|
if ((i_length + 4) == 100)
|
check_tx_packet(`MEMORY_BASE, 0, 100 - 4, tmp);
|
check_tx_packet(`MEMORY_BASE, 0, 100 - 4, tmp);
|
else if ((i_length + 4) <= max_tmp)
|
else if ((i_length + 4) <= max_tmp)
|
| Line 8121... |
Line 8270... |
`TIME; $display("*E WB INT signal should be set");
|
`TIME; $display("*E WB INT signal should be set");
|
test_fail("WB INT signal should be set");
|
test_fail("WB INT signal should be set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
|
|
check_tx_bd(num_of_bd, data);
|
check_tx_bd(tx_bd_num, data);
|
if ( ((data[15:0] !== 16'h7800) && (num_of_bd == 2)) || // wrap bit
|
if ( ((data[15:0] !== 16'h7800) && (num_of_bd == 2)) || // wrap bit
|
((data[15:0] !== 16'h5800) && (num_of_bd < 2)) ) // without wrap bit
|
((data[15:0] !== 16'h5800) && (num_of_bd < 2)) ) // without wrap bit
|
begin
|
begin
|
`TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
|
`TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
|
test_fail("TX buffer descriptor status is not correct");
|
test_fail("TX buffer descriptor status is not correct");
|
| Line 8205... |
Line 8354... |
|
|
max_tmp = 0;
|
max_tmp = 0;
|
min_tmp = 0;
|
min_tmp = 0;
|
num_of_frames = 0;
|
num_of_frames = 0;
|
num_of_bd = 0;
|
num_of_bd = 0;
|
|
tx_bd_num = 0;
|
// set 13 TX buffer descriptors - must be set before TX enable
|
// set 13 TX buffer descriptors - must be set before TX enable
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_write(`ETH_TX_BD_NUM, 32'hD, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_write(`ETH_TX_BD_NUM, 32'hD, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
// enable TX, set full-duplex mode, NO padding and CRC appending
|
// enable TX, set full-duplex mode, NO padding and CRC appending
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
| Line 8253... |
Line 8403... |
set_tx_bd(2, 2, i_length+2, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
|
set_tx_bd(2, 2, i_length+2, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
|
set_tx_bd_wrap(2);
|
set_tx_bd_wrap(2);
|
set_tx_bd_ready(0, 0);
|
set_tx_bd_ready(0, 0);
|
end
|
end
|
else if (num_of_bd == 1)
|
else if (num_of_bd == 1)
|
|
begin
|
set_tx_bd_ready(1, 1);
|
set_tx_bd_ready(1, 1);
|
|
tx_bd_num = 1;
|
|
end
|
else if (num_of_bd == 2)
|
else if (num_of_bd == 2)
|
|
begin
|
set_tx_bd_ready(2, 2);
|
set_tx_bd_ready(2, 2);
|
|
tx_bd_num = 2;
|
|
end
|
else if (num_of_bd == 3)
|
else if (num_of_bd == 3)
|
begin
|
begin
|
set_tx_bd(0, 0, 100, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
|
set_tx_bd(0, 0, 100, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
|
set_tx_bd_wrap(2);
|
set_tx_bd_wrap(2);
|
set_tx_bd_ready(0, 0);
|
set_tx_bd_ready(0, 0);
|
i_length = 96;
|
i_length = 100;
|
|
tx_bd_num = 0;
|
end
|
end
|
|
|
|
|
// CHECK END OF TRANSMITION
|
// CHECK END OF TRANSMITION
|
check_tx_bd(num_of_bd, data);
|
check_tx_bd(tx_bd_num, data);
|
wait (MTxEn === 1'b1); // start transmit
|
wait (MTxEn === 1'b1); // start transmit
|
check_tx_bd(num_of_bd, data);
|
check_tx_bd(tx_bd_num, data);
|
if (data[15] !== 1)
|
if (data[15] !== 1)
|
begin
|
begin
|
test_fail("Wrong buffer descriptor's ready bit read out from MAC");
|
test_fail("Wrong buffer descriptor's ready bit read out from MAC");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
wait (MTxEn === 1'b0); // end transmit
|
wait (MTxEn === 1'b0); // end transmit
|
while (data[15] === 1)
|
while (data[15] === 1)
|
begin
|
begin
|
check_tx_bd(num_of_bd, data);
|
check_tx_bd(tx_bd_num, data);
|
@(posedge wb_clk);
|
@(posedge wb_clk);
|
end
|
end
|
repeat (1) @(posedge wb_clk);
|
repeat (1) @(posedge wb_clk);
|
repeat (10) @(posedge mtx_clk);
|
repeat (10) @(posedge mtx_clk);
|
// check length of a PACKET
|
// check length of a PACKET
|
tmp_len = eth_phy.tx_len;
|
tmp_len = eth_phy.tx_len;
|
#1;
|
#1;
|
|
if ((i_length + 4) <= max_tmp)
|
|
begin
|
if (tmp_len != (i_length + 4))
|
if (tmp_len != (i_length + 4))
|
begin
|
begin
|
test_fail("Wrong length of the packet out from MAC");
|
test_fail("Wrong length of the packet out from MAC");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
|
end
|
|
else
|
|
begin
|
|
if (tmp_len != (i_length + 4 - 1))
|
|
begin
|
|
test_fail("Wrong length of the packet out from MAC");
|
|
fail = fail + 1;
|
|
end
|
|
end
|
|
|
// check transmitted TX packet data
|
// check transmitted TX packet data
|
if ((i_length + 4) == 100)
|
if ((i_length + 4) == 100)
|
check_tx_packet(`MEMORY_BASE, 0, 100 - 4, tmp);
|
check_tx_packet(`MEMORY_BASE, 0, 100 - 4, tmp);
|
else if ((i_length + 4) <= max_tmp)
|
else if ((i_length + 4) <= max_tmp)
|
| Line 8324... |
Line 8492... |
`TIME; $display("*E WB INT signal should be set");
|
`TIME; $display("*E WB INT signal should be set");
|
test_fail("WB INT signal should be set");
|
test_fail("WB INT signal should be set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
|
|
check_tx_bd(num_of_bd, data);
|
check_tx_bd(tx_bd_num, data);
|
if ( ((data[15:0] !== 16'h7800) && (num_of_bd == 2)) || // wrap bit
|
if ( ((data[15:0] !== 16'h7800) && (num_of_bd == 2)) || // wrap bit
|
((data[15:0] !== 16'h5800) && (num_of_bd < 2)) ) // without wrap bit
|
((data[15:0] !== 16'h5800) && (num_of_bd < 2)) ) // without wrap bit
|
begin
|
begin
|
`TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
|
`TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
|
test_fail("TX buffer descriptor status is not correct");
|
test_fail("TX buffer descriptor status is not correct");
|
| Line 8409... |
Line 8577... |
|
|
max_tmp = 0;
|
max_tmp = 0;
|
min_tmp = 0;
|
min_tmp = 0;
|
num_of_frames = 0;
|
num_of_frames = 0;
|
num_of_bd = 0;
|
num_of_bd = 0;
|
|
tx_bd_num = 0;
|
// set 47 TX buffer descriptors - must be set before TX enable
|
// set 47 TX buffer descriptors - must be set before TX enable
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_write(`ETH_TX_BD_NUM, 32'h2F, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_write(`ETH_TX_BD_NUM, 32'h2F, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
// prepare a packet of MAXFL + 10 length
|
// prepare a packet of MAXFL + 10 length
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
| Line 8452... |
Line 8621... |
// first destination address on ethernet PHY
|
// first destination address on ethernet PHY
|
eth_phy.set_tx_mem_addr(0);
|
eth_phy.set_tx_mem_addr(0);
|
// prepare BDs
|
// prepare BDs
|
if (num_of_bd == 0)
|
if (num_of_bd == 0)
|
begin
|
begin
|
set_tx_bd(0, 0, i_length, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
|
set_tx_bd(0, 0, i_length+4, 1'b1, 1'b1, 1'b0, `MEMORY_BASE); // no CRC adding
|
set_tx_bd(1, 1, i_length+1, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
|
set_tx_bd(1, 1, i_length+1, 1'b1, 1'b0, 1'b1, `MEMORY_BASE); // no PADDING
|
set_tx_bd(2, 2, i_length+2, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
|
set_tx_bd(2, 2, i_length+2, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
|
set_tx_bd_wrap(2);
|
set_tx_bd_wrap(2);
|
set_tx_bd_ready(0, 0);
|
set_tx_bd_ready(0, 0);
|
end
|
end
|
else if (num_of_bd == 1)
|
else if (num_of_bd == 1)
|
|
begin
|
set_tx_bd_ready(1, 1);
|
set_tx_bd_ready(1, 1);
|
|
tx_bd_num = 1;
|
|
end
|
else if (num_of_bd == 2)
|
else if (num_of_bd == 2)
|
|
begin
|
set_tx_bd_ready(2, 2);
|
set_tx_bd_ready(2, 2);
|
|
tx_bd_num = 2;
|
|
end
|
// CHECK END OF TRANSMITION
|
// CHECK END OF TRANSMITION
|
check_tx_bd(num_of_bd, data);
|
check_tx_bd(tx_bd_num, data);
|
wait (MTxEn === 1'b1); // start transmit
|
wait (MTxEn === 1'b1); // start transmit
|
check_tx_bd(num_of_bd, data);
|
check_tx_bd(tx_bd_num, data);
|
if (data[15] !== 1)
|
if (data[15] !== 1)
|
begin
|
begin
|
test_fail("Wrong buffer descriptor's ready bit read out from MAC");
|
test_fail("Wrong buffer descriptor's ready bit read out from MAC");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
wait (MTxEn === 1'b0); // end transmit
|
wait (MTxEn === 1'b0); // end transmit
|
while (data[15] === 1)
|
while (data[15] === 1)
|
begin
|
begin
|
check_tx_bd(num_of_bd, data);
|
check_tx_bd(tx_bd_num, data);
|
@(posedge wb_clk);
|
@(posedge wb_clk);
|
end
|
end
|
repeat (5) @(posedge mtx_clk);
|
repeat (5) @(posedge mtx_clk);
|
// check length of a PACKET
|
// check length of a PACKET
|
tmp_len = eth_phy.tx_len;
|
tmp_len = eth_phy.tx_len;
|
#1;
|
#1;
|
|
if ((i_length + 4) <= max_tmp)
|
|
begin
|
if (tmp_len != (i_length + 4))
|
if (tmp_len != (i_length + 4))
|
begin
|
begin
|
test_fail("Wrong length of the packet out from MAC");
|
test_fail("Wrong length of the packet out from MAC");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
|
end
|
|
else
|
|
begin
|
|
if (tmp_len != (i_length + 4 - 1))
|
|
begin
|
|
test_fail("Wrong length of the packet out from MAC");
|
|
fail = fail + 1;
|
|
end
|
|
end
|
|
|
// checking packet
|
// checking packet
|
|
if (num_of_bd === 0)
|
|
check_tx_packet(`MEMORY_BASE, 0, i_length + 4, tmp); // also data representing CRC
|
|
else
|
check_tx_packet(`MEMORY_BASE, 0, i_length, tmp);
|
check_tx_packet(`MEMORY_BASE, 0, i_length, tmp);
|
if (tmp > 0)
|
if (tmp > 0)
|
begin
|
begin
|
test_fail("Wrong data of the transmitted packet");
|
test_fail("Wrong data of the transmitted packet");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
// check transmited TX packet CRC
|
// check transmited TX packet CRC
|
if (num_of_bd !== 2)
|
if (num_of_bd === 1)
|
check_tx_crc(0, i_length, 1'b0, tmp); // length without CRC
|
check_tx_crc(0, i_length, 1'b0, tmp); // length without CRC
|
if (tmp > 0)
|
if (tmp > 0)
|
begin
|
begin
|
test_fail("Wrong CRC of the transmitted packet");
|
test_fail("Wrong CRC of the transmitted packet");
|
fail = fail + 1;
|
fail = fail + 1;
|
| Line 8509... |
Line 8699... |
`TIME; $display("*E WB INT signal should be set");
|
`TIME; $display("*E WB INT signal should be set");
|
test_fail("WB INT signal should be set");
|
test_fail("WB INT signal should be set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
// check TX buffer descriptor of a packet
|
// check TX buffer descriptor of a packet
|
check_tx_bd(num_of_bd, data);
|
check_tx_bd(tx_bd_num, data);
|
if ( ((data[15:0] !== 16'h7800) && (num_of_bd == 2)) || // wrap bit
|
if ( ((data[15:0] !== 16'h7800) && (num_of_bd == 2)) || // wrap bit
|
((data[15:0] !== 16'h5800) && (num_of_bd < 2)) ) // without wrap bit
|
((data[15:0] !== 16'h4800) && (num_of_bd == 1)) || // without wrap bit and without pad bit
|
|
((data[15:0] !== 16'h5000) && (num_of_bd == 0)) ) // without wrap bit and without crc bit
|
begin
|
begin
|
`TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
|
`TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
|
test_fail("TX buffer descriptor status is not correct");
|
test_fail("TX buffer descriptor status is not correct");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
| Line 8587... |
Line 8778... |
|
|
max_tmp = 0;
|
max_tmp = 0;
|
min_tmp = 0;
|
min_tmp = 0;
|
num_of_frames = 0;
|
num_of_frames = 0;
|
num_of_bd = 0;
|
num_of_bd = 0;
|
|
tx_bd_num = 0;
|
// set 47 TX buffer descriptors - must be set before TX enable
|
// set 47 TX buffer descriptors - must be set before TX enable
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
wbm_write(`ETH_TX_BD_NUM, 32'h2F, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_write(`ETH_TX_BD_NUM, 32'h2F, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
// prepare a packet of MAXFL + 10 length
|
// prepare a packet of MAXFL + 10 length
|
wait (wbm_working == 0);
|
wait (wbm_working == 0);
|
| Line 8630... |
Line 8822... |
// first destination address on ethernet PHY
|
// first destination address on ethernet PHY
|
eth_phy.set_tx_mem_addr(0);
|
eth_phy.set_tx_mem_addr(0);
|
// prepare BDs
|
// prepare BDs
|
if (num_of_bd == 0)
|
if (num_of_bd == 0)
|
begin
|
begin
|
set_tx_bd(0, 0, i_length, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
|
set_tx_bd(0, 0, i_length+4, 1'b1, 1'b1, 1'b0, `MEMORY_BASE); // no CRC adding
|
set_tx_bd(1, 1, i_length+1, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
|
set_tx_bd(1, 1, i_length+1, 1'b1, 1'b0, 1'b1, `MEMORY_BASE); // no PADDING
|
set_tx_bd(2, 2, i_length+2, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
|
set_tx_bd(2, 2, i_length+2, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
|
set_tx_bd_wrap(2);
|
set_tx_bd_wrap(2);
|
set_tx_bd_ready(0, 0);
|
set_tx_bd_ready(0, 0);
|
end
|
end
|
else if (num_of_bd == 1)
|
else if (num_of_bd == 1)
|
|
begin
|
set_tx_bd_ready(1, 1);
|
set_tx_bd_ready(1, 1);
|
|
tx_bd_num = 1;
|
|
end
|
else if (num_of_bd == 2)
|
else if (num_of_bd == 2)
|
|
begin
|
set_tx_bd_ready(2, 2);
|
set_tx_bd_ready(2, 2);
|
|
tx_bd_num = 2;
|
|
end
|
// CHECK END OF TRANSMITION
|
// CHECK END OF TRANSMITION
|
check_tx_bd(num_of_bd, data);
|
check_tx_bd(tx_bd_num, data);
|
wait (MTxEn === 1'b1); // start transmit
|
wait (MTxEn === 1'b1); // start transmit
|
check_tx_bd(num_of_bd, data);
|
check_tx_bd(tx_bd_num, data);
|
if (data[15] !== 1)
|
if (data[15] !== 1)
|
begin
|
begin
|
test_fail("Wrong buffer descriptor's ready bit read out from MAC");
|
test_fail("Wrong buffer descriptor's ready bit read out from MAC");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
wait (MTxEn === 1'b0); // end transmit
|
wait (MTxEn === 1'b0); // end transmit
|
while (data[15] === 1)
|
while (data[15] === 1)
|
begin
|
begin
|
check_tx_bd(num_of_bd, data);
|
check_tx_bd(tx_bd_num, data);
|
@(posedge wb_clk);
|
@(posedge wb_clk);
|
end
|
end
|
repeat (5) @(posedge mtx_clk);
|
repeat (5) @(posedge mtx_clk);
|
// check length of a PACKET
|
// check length of a PACKET
|
tmp_len = eth_phy.tx_len;
|
tmp_len = eth_phy.tx_len;
|
#1;
|
#1;
|
|
if ((i_length + 4) <= max_tmp)
|
|
begin
|
if (tmp_len != (i_length + 4))
|
if (tmp_len != (i_length + 4))
|
begin
|
begin
|
test_fail("Wrong length of the packet out from MAC");
|
test_fail("Wrong length of the packet out from MAC");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
|
end
|
|
else
|
|
begin
|
|
if (tmp_len != (i_length + 4 - 1))
|
|
begin
|
|
test_fail("Wrong length of the packet out from MAC");
|
|
fail = fail + 1;
|
|
end
|
|
end
|
|
|
// checking packet
|
// checking packet
|
|
if (num_of_bd === 0)
|
|
check_tx_packet(`MEMORY_BASE, 0, i_length + 4, tmp); // also data representing CRC
|
|
else
|
check_tx_packet(`MEMORY_BASE, 0, i_length, tmp);
|
check_tx_packet(`MEMORY_BASE, 0, i_length, tmp);
|
if (tmp > 0)
|
if (tmp > 0)
|
begin
|
begin
|
test_fail("Wrong data of the transmitted packet");
|
test_fail("Wrong data of the transmitted packet");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
// check transmited TX packet CRC
|
// check transmited TX packet CRC
|
if (num_of_bd !== 2)
|
if (num_of_bd === 1)
|
check_tx_crc(0, i_length, 1'b0, tmp); // length without CRC
|
check_tx_crc(0, i_length, 1'b0, tmp); // length without CRC
|
if (tmp > 0)
|
if (tmp > 0)
|
begin
|
begin
|
test_fail("Wrong CRC of the transmitted packet");
|
test_fail("Wrong CRC of the transmitted packet");
|
fail = fail + 1;
|
fail = fail + 1;
|
| Line 8687... |
Line 8900... |
`TIME; $display("*E WB INT signal should be set");
|
`TIME; $display("*E WB INT signal should be set");
|
test_fail("WB INT signal should be set");
|
test_fail("WB INT signal should be set");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
// check TX buffer descriptor of a packet
|
// check TX buffer descriptor of a packet
|
check_tx_bd(num_of_bd, data);
|
check_tx_bd(tx_bd_num, data);
|
if ( ((data[15:0] !== 16'h7800) && (num_of_bd == 2)) || // wrap bit
|
if ( ((data[15:0] !== 16'h7800) && (num_of_bd == 2)) || // wrap bit
|
((data[15:0] !== 16'h5800) && (num_of_bd < 2)) ) // without wrap bit
|
((data[15:0] !== 16'h4800) && (num_of_bd == 1)) || // without wrap bit and without pad bit
|
|
((data[15:0] !== 16'h5000) && (num_of_bd == 0)) ) // without wrap bit and without crc bit
|
begin
|
begin
|
`TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
|
`TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
|
test_fail("TX buffer descriptor status is not correct");
|
test_fail("TX buffer descriptor status is not correct");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
| Line 8843... |
Line 9057... |
end
|
end
|
repeat (1) @(posedge wb_clk);
|
repeat (1) @(posedge wb_clk);
|
// check length of a PACKET
|
// check length of a PACKET
|
tmp_len = eth_phy.tx_len;
|
tmp_len = eth_phy.tx_len;
|
#1;
|
#1;
|
|
if ((i_length + 4) >= min_tmp)
|
|
begin
|
if (tmp_len != (i_length + 4))
|
if (tmp_len != (i_length + 4))
|
begin
|
begin
|
test_fail("Wrong length of the packet out from MAC");
|
test_fail("Wrong length of the packet out from MAC");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
|
end
|
|
else
|
|
begin
|
|
if (tmp_len != (i_length + 4 + 1))
|
|
begin
|
|
test_fail("Wrong length of the packet out from MAC");
|
|
fail = fail + 1;
|
|
end
|
|
end
|
// checking packet
|
// checking packet
|
check_tx_packet(`MEMORY_BASE, 0, i_length, tmp);
|
check_tx_packet(`MEMORY_BASE, 0, i_length, tmp);
|
if (tmp > 0)
|
if (tmp > 0)
|
begin
|
begin
|
test_fail("Wrong data of the transmitted packet");
|
test_fail("Wrong data of the transmitted packet");
|
| Line 9026... |
Line 9251... |
end
|
end
|
repeat (1) @(posedge wb_clk);
|
repeat (1) @(posedge wb_clk);
|
// check length of a PACKET
|
// check length of a PACKET
|
tmp_len = eth_phy.tx_len;
|
tmp_len = eth_phy.tx_len;
|
#1;
|
#1;
|
|
if ((i_length + 4) >= min_tmp)
|
|
begin
|
if (tmp_len != (i_length + 4))
|
if (tmp_len != (i_length + 4))
|
begin
|
begin
|
test_fail("Wrong length of the packet out from MAC");
|
test_fail("Wrong length of the packet out from MAC");
|
fail = fail + 1;
|
fail = fail + 1;
|
end
|
end
|
|
end
|
|
else
|
|
begin
|
|
if (tmp_len != (i_length + 4 + 1))
|
|
begin
|
|
test_fail("Wrong length of the packet out from MAC");
|
|
fail = fail + 1;
|
|
end
|
|
end
|
// checking packet
|
// checking packet
|
check_tx_packet(`MEMORY_BASE, 0, i_length, tmp);
|
check_tx_packet(`MEMORY_BASE, 0, i_length, tmp);
|
if (tmp > 0)
|
if (tmp > 0)
|
begin
|
begin
|
test_fail("Wrong data of the transmitted packet");
|
test_fail("Wrong data of the transmitted packet");
|
| Line 18451... |
Line 18687... |
wb_slave.wr_mem(addr_wb - 3, {24'h0, crc[7:0]}, 4'h1);
|
wb_slave.wr_mem(addr_wb - 3, {24'h0, crc[7:0]}, 4'h1);
|
wb_slave.wr_mem(addr_wb + 1, {crc[15:8], crc[23:16], crc[31:24], 8'h0}, 4'hE);
|
wb_slave.wr_mem(addr_wb + 1, {crc[15:8], crc[23:16], crc[31:24], 8'h0}, 4'hE);
|
end
|
end
|
else
|
else
|
begin
|
begin
|
wb_slave.wr_mem(addr_wb, {crc[7:0], crc[15:8], crc[23:16], crc[31:24]}, 4'hF);
|
// wb_slave.wr_mem(addr_wb, {crc[7:0], crc[15:8], crc[23:16], crc[31:24]}, 4'hF);
|
|
wb_slave.wr_mem(addr_wb, crc[31:0], 4'hF);
|
end
|
end
|
delta_t = !delta_t;
|
delta_t = !delta_t;
|
end
|
end
|
endtask // append_tx_crc
|
endtask // append_tx_crc
|
|
|
| Line 18827... |
Line 19064... |
// get number of nibbles from Byte length (2^1 = 2)
|
// get number of nibbles from Byte length (2^1 = 2)
|
if (plus_dribble_nibble)
|
if (plus_dribble_nibble)
|
nibble_cnt = ((len + 4) << 1) + 1'b1; // one nibble longer
|
nibble_cnt = ((len + 4) << 1) + 1'b1; // one nibble longer
|
else
|
else
|
nibble_cnt = ((len + 4) << 1);
|
nibble_cnt = ((len + 4) << 1);
|
load_reg = wb_slave.wb_memory[{12'h0, addr_cnt}];
|
load_reg = wb_slave.wb_memory[{12'h0, addr_cnt[21:2]}];
|
addr_cnt = addr_cnt + 4;
|
addr_cnt = addr_cnt + 4;
|
while (nibble_cnt > 0)
|
while (nibble_cnt > 0)
|
begin
|
begin
|
// wait for delta time
|
// wait for delta time
|
delta_t = !delta_t;
|
delta_t = !delta_t;
|
| Line 18888... |
Line 19125... |
delta_t = !delta_t;
|
delta_t = !delta_t;
|
// increment address and load new data
|
// increment address and load new data
|
if ((word_cnt+3) == 7)//4)
|
if ((word_cnt+3) == 7)//4)
|
begin
|
begin
|
// because of MAGIC NUMBER nibbles are swapped [3:0] -> [0:3]
|
// because of MAGIC NUMBER nibbles are swapped [3:0] -> [0:3]
|
load_reg = wb_slave.wb_memory[{12'h0, addr_cnt}];
|
load_reg = wb_slave.wb_memory[{12'h0, addr_cnt[21:2]}];
|
addr_cnt = addr_cnt + 4;
|
addr_cnt = addr_cnt + 4;
|
end
|
end
|
// set new load bit position
|
// set new load bit position
|
if((word_cnt+3) == 31)
|
if((word_cnt+3) == 31)
|
word_cnt = 16;
|
word_cnt = 16;
|
| Line 19492... |
Line 19729... |
`endif
|
`endif
|
end
|
end
|
endtask // test_fail
|
endtask // test_fail
|
|
|
|
|
|
task test_fail_num ;
|
|
input [7999:0] failure_reason ;
|
|
input [31:0] number ;
|
|
// reg [8007:0] display_failure ;
|
|
reg [7999:0] display_failure ;
|
|
reg [799:0] display_test ;
|
|
begin
|
|
tests_failed = tests_failed + 1 ;
|
|
|
|
display_failure = failure_reason; // {failure_reason, "!"} ;
|
|
while ( display_failure[7999:7992] == 0 )
|
|
display_failure = display_failure << 8 ;
|
|
|
|
display_test = test_name ;
|
|
while ( display_test[799:792] == 0 )
|
|
display_test = display_test << 8 ;
|
|
|
|
$fdisplay( tb_log_file, " *************************************************************************************" ) ;
|
|
$fdisplay( tb_log_file, " At time: %t ", $time ) ;
|
|
$fdisplay( tb_log_file, " Test: %s", display_test ) ;
|
|
$fdisplay( tb_log_file, " *FAILED* because") ;
|
|
$fdisplay( tb_log_file, " %s; %d", display_failure, number ) ;
|
|
$fdisplay( tb_log_file, " *************************************************************************************" ) ;
|
|
$fdisplay( tb_log_file, " " ) ;
|
|
|
|
`ifdef STOP_ON_FAILURE
|
|
#20 $stop ;
|
|
`endif
|
|
end
|
|
endtask // test_fail_num
|
|
|
|
|
task test_ok ;
|
task test_ok ;
|
reg [799:0] display_test ;
|
reg [799:0] display_test ;
|
begin
|
begin
|
tests_successfull = tests_successfull + 1 ;
|
tests_successfull = tests_successfull + 1 ;
|
|
|
