Line 1... |
Line 1... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// File name "wb_master_behavioral.v" ////
|
//// File name "wb_master_behavioral.v" ////
|
//// ////
|
//// ////
|
//// This file is part of the "PCI bridge" project ////
|
//// This file is part of the Ethernet IP core project ////
|
//// http://www.opencores.org/cores/pci/ ////
|
//// http://www.opencores.org/projects/ethmac/ ////
|
//// ////
|
//// ////
|
//// Author(s): ////
|
//// Author(s): ////
|
//// - Miha Dolenc (mihad@opencores.org) ////
|
//// - Miha Dolenc (mihad@opencores.org) ////
|
//// ////
|
//// ////
|
|
//// All additional information is available in the Readme.txt ////
|
|
//// file. ////
|
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Copyright (C) 2000 Miha Dolenc, mihad@opencores.org ////
|
//// Copyright (C) 2002 Authors ////
|
//// ////
|
//// ////
|
//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
|
//// restriction provided that this copyright statement is not ////
|
//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// the original copyright notice and the associated disclaimer. ////
|
Line 36... |
Line 39... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.1 2002/09/13 11:57:20 mohor
|
|
// New testbench. Thanks to Tadej M - "The Spammer".
|
|
//
|
// Revision 1.1 2002/07/29 11:25:20 mihad
|
// Revision 1.1 2002/07/29 11:25:20 mihad
|
// Adding test bench for memory interface
|
// Adding test bench for memory interface
|
//
|
//
|
// Revision 1.1 2002/02/01 13:39:43 mihad
|
// Revision 1.1 2002/02/01 13:39:43 mihad
|
// Initial testbench import. Still under development
|
// Initial testbench import. Still under development
|