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[/] [ethmac/] [trunk/] [bench/] [verilog/] [wb_slave_behavioral.v] - Diff between revs 170 and 318
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| Rev 170 |
Rev 318 |
| Line 40... |
Line 40... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2002/09/13 12:29:14 mohor
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// Headers changed.
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//
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// Revision 1.1 2002/09/13 11:57:21 mohor
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// Revision 1.1 2002/09/13 11:57:21 mohor
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// New testbench. Thanks to Tadej M - "The Spammer".
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// New testbench. Thanks to Tadej M - "The Spammer".
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//
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//
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// Revision 1.2 2002/03/06 09:10:56 mihad
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// Revision 1.2 2002/03/06 09:10:56 mihad
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// Added missing include statements
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// Added missing include statements
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task_mem_wr_data[ 7: 0] = task_dat_i[ 7: 0];
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task_mem_wr_data[ 7: 0] = task_dat_i[ 7: 0];
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wb_memory[task_wr_adr_i[21:2]] = task_mem_wr_data; // write data
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wb_memory[task_wr_adr_i[21:2]] = task_mem_wr_data; // write data
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task_data_written = 1;
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task_data_written = 1;
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end
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end
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else if (wr_sel && CLK_I)
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else if (wr_sel && ~CLK_I)
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begin
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begin
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// mem_wr_data_out = wb_memory[ADR_I[25:2]]; // if no SEL_I is active, old value will be written
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// mem_wr_data_out = wb_memory[ADR_I[25:2]]; // if no SEL_I is active, old value will be written
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mem_wr_data_out = wb_memory[ADR_I[21:2]]; // if no SEL_I is active, old value will be written
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mem_wr_data_out = wb_memory[ADR_I[21:2]]; // if no SEL_I is active, old value will be written
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if (SEL_I[3])
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if (SEL_I[3])
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