URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_clockgen.v] - Diff between revs 37 and 330

Rev 37	Rev 330
Line 39...	Line 39...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.3 2002/01/23 10:28:16 mohor`
	`// Link in the header changed.`
	`//`
`// Revision 1.2 2001/10/19 08:43:51 mohor`	`// Revision 1.2 2001/10/19 08:43:51 mohor`
`// eth_timescale.v changed to timescale.v This is done because of the`	`// eth_timescale.v changed to timescale.v This is done because of the`
`// simulation of the few cores in a one joined project.`	`// simulation of the few cores in a one joined project.`
`//`	`//`
`// Revision 1.1 2001/08/06 14:44:29 mohor`	`// Revision 1.1 2001/08/06 14:44:29 mohor`
Line 84...	Line 87...
`wire [7:0] CounterPreset;`	`wire [7:0] CounterPreset;`
`wire [7:0] TempDivider;`	`wire [7:0] TempDivider;`


`assign TempDivider[7:0] = (Divider[7:0]<2)? 8'h02 : Divider[7:0]; // If smaller than 2`	`assign TempDivider[7:0] = (Divider[7:0]<2)? 8'h02 : Divider[7:0]; // If smaller than 2`
`assign CounterPreset[7:0] = (TempDivider[7:0]>>1) -1; // We are counting half of period`	`assign CounterPreset[7:0] = (TempDivider[7:0]>>1) - 1'b1; // We are counting half of period`


`// Counter counts half period`	`// Counter counts half period`
`always @ (posedge Clk or posedge Reset)`	`always @ (posedge Clk or posedge Reset)`
`begin`	`begin`