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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_clockgen.v] - Diff between revs 352 and 353
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| Rev 352 |
Rev 353 |
| Line 85... |
Line 85... |
wire [7:0] CounterPreset;
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wire [7:0] CounterPreset;
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wire [7:0] TempDivider;
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wire [7:0] TempDivider;
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assign TempDivider[7:0] = (Divider[7:0]<2)? 8'h02 : Divider[7:0]; // If smaller than 2
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assign TempDivider[7:0] = (Divider[7:0]<2)? 8'h02 : Divider[7:0]; // If smaller than 2
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assign CounterPreset[7:0] = (TempDivider[7:0]>>1) - 1'b1; // We are counting half of period
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assign CounterPreset[7:0] = (TempDivider[7:0]>>1) - 8'b1; // We are counting half of period
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// Counter counts half period
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// Counter counts half period
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always @ (posedge Clk or posedge Reset)
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always @ (posedge Clk or posedge Reset)
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begin
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begin
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