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//
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//
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//
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//
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//
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//
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//
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//
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`include "eth_defines.v"
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`include "timescale.v"
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`include "timescale.v"
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module eth_cop
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module eth_cop
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(
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(
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// WISHBONE common
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// WISHBONE common
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s2_wb_stb_o, s2_wb_ack_i, s2_wb_err_i, s2_wb_dat_i,
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s2_wb_stb_o, s2_wb_ack_i, s2_wb_err_i, s2_wb_dat_i,
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s2_wb_dat_o
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s2_wb_dat_o
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);
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);
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parameter Tp=1;
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parameter Tp=1;
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parameter ETH_BASE = 32'hd0000000;
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parameter ETH_WIDTH = 32'h800;
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parameter MEMORY_BASE = 32'h2000;
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parameter MEMORY_WIDTH = 32'h10000;
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// WISHBONE common
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// WISHBONE common
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input wb_clk_i, wb_rst_i;
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input wb_clk_i, wb_rst_i;
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// WISHBONE MASTER 1
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// WISHBONE MASTER 1
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reg m1_wb_err_o;
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reg m1_wb_err_o;
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reg m2_wb_err_o;
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reg m2_wb_err_o;
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wire m_wb_access_finished;
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wire m_wb_access_finished;
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wire m1_addressed_s1 = (m1_wb_adr_i >= `ETH_BASE) &
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wire m1_addressed_s1 = (m1_wb_adr_i >= ETH_BASE) &
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(m1_wb_adr_i < (`ETH_BASE + `ETH_WIDTH));
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(m1_wb_adr_i < (ETH_BASE + ETH_WIDTH));
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wire m1_addressed_s2 = (m1_wb_adr_i >= `MEMORY_BASE) &
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wire m1_addressed_s2 = (m1_wb_adr_i >= MEMORY_BASE) &
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(m1_wb_adr_i < (`MEMORY_BASE + `MEMORY_WIDTH));
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(m1_wb_adr_i < (MEMORY_BASE + MEMORY_WIDTH));
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wire m2_addressed_s1 = (m2_wb_adr_i >= `ETH_BASE) &
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wire m2_addressed_s1 = (m2_wb_adr_i >= ETH_BASE) &
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(m2_wb_adr_i < (`ETH_BASE + `ETH_WIDTH));
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(m2_wb_adr_i < (ETH_BASE + ETH_WIDTH));
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wire m2_addressed_s2 = (m2_wb_adr_i >= `MEMORY_BASE) &
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wire m2_addressed_s2 = (m2_wb_adr_i >= MEMORY_BASE) &
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(m2_wb_adr_i < (`MEMORY_BASE + `MEMORY_WIDTH));
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(m2_wb_adr_i < (MEMORY_BASE + MEMORY_WIDTH));
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wire m1_req = m1_wb_cyc_i & m1_wb_stb_i & (m1_addressed_s1 | m1_addressed_s2);
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wire m1_req = m1_wb_cyc_i & m1_wb_stb_i & (m1_addressed_s1 | m1_addressed_s2);
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wire m2_req = m2_wb_cyc_i & m2_wb_stb_i & (m2_addressed_s1 | m2_addressed_s2);
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wire m2_req = m2_wb_cyc_i & m2_wb_stb_i & (m2_addressed_s1 | m2_addressed_s2);
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always @ (posedge wb_clk_i or posedge wb_rst_i)
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always @ (posedge wb_clk_i or posedge wb_rst_i)
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