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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_crc.v] - Diff between revs 346 and 352
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| Rev 346 |
Rev 352 |
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Line 77... |
`include "timescale.v"
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`include "timescale.v"
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module eth_crc (Clk, Reset, Data, Enable, Initialize, Crc, CrcError);
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module eth_crc (Clk, Reset, Data, Enable, Initialize, Crc, CrcError);
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parameter Tp = 1;
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input Clk;
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input Clk;
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input Reset;
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input Reset;
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input [3:0] Data;
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input [3:0] Data;
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input Enable;
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input Enable;
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input Initialize;
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input Initialize;
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Line 128... |
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always @ (posedge Clk or posedge Reset)
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always @ (posedge Clk or posedge Reset)
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begin
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begin
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if (Reset)
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if (Reset)
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Crc <= #1 32'hffffffff;
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Crc <= 32'hffffffff;
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else
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else
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if(Initialize)
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if(Initialize)
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Crc <= #Tp 32'hffffffff;
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Crc <= 32'hffffffff;
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else
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else
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Crc <= #Tp CrcNext;
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Crc <= CrcNext;
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end
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end
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assign CrcError = Crc[31:0] != 32'hc704dd7b; // CRC not equal to magic number
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assign CrcError = Crc[31:0] != 32'hc704dd7b; // CRC not equal to magic number
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endmodule
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endmodule
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