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Line 39... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.3 2002/04/22 13:45:52 mohor
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// Generic ram or Xilinx ram can be used in fifo (selectable by setting
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// ETH_FIFO_XILINX in eth_defines.v).
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//
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// Revision 1.2 2002/03/25 13:33:04 mohor
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// Revision 1.2 2002/03/25 13:33:04 mohor
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// When clear and read/write are active at the same time, cnt and pointers are
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// When clear and read/write are active at the same time, cnt and pointers are
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// set to 1.
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// set to 1.
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//
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//
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// Revision 1.1 2002/02/05 16:44:39 mohor
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// Revision 1.1 2002/02/05 16:44:39 mohor
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Line 81... |
output empty;
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output empty;
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output [CNT_WIDTH-1:0] cnt;
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output [CNT_WIDTH-1:0] cnt;
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`ifdef ETH_FIFO_XILINX
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`ifdef ETH_FIFO_XILINX
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`else
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`else
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`ifdef ETH_ALTERA_ALTSYNCRAM
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`else
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reg [DATA_WIDTH-1:0] fifo [0:DEPTH-1];
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reg [DATA_WIDTH-1:0] fifo [0:DEPTH-1];
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reg [DATA_WIDTH-1:0] data_out;
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`endif
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`endif
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`endif
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reg [CNT_WIDTH-1:0] cnt;
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reg [CNT_WIDTH-1:0] cnt;
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reg [CNT_WIDTH-2:0] read_pointer;
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reg [CNT_WIDTH-2:0] read_pointer;
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reg [CNT_WIDTH-2:0] write_pointer;
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reg [CNT_WIDTH-2:0] write_pointer;
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Line 148... |
.data_in(data_in),
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.data_in(data_in),
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.read_address( clear ? {CNT_WIDTH-1{1'b0}} : read_pointer),
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.read_address( clear ? {CNT_WIDTH-1{1'b0}} : read_pointer),
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.write_address(clear ? {CNT_WIDTH-1{1'b0}} : write_pointer),
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.write_address(clear ? {CNT_WIDTH-1{1'b0}} : write_pointer),
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.wclk(clk)
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.wclk(clk)
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);
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);
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`else
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`else // !ETH_FIFO_XILINX
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`ifdef ETH_ALTERA_ALTSYNCRAM
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altera_dpram_16x32 altera_dpram_16x32_inst
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(
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.data (data_in),
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.wren (write & ~full),
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.wraddress (clear ? {CNT_WIDTH-1{1'b0}} : write_pointer),
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.rdaddress (clear ? {CNT_WIDTH-1{1'b0}} : read_pointer ),
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.clock (clk),
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.q (data_out)
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); //exemplar attribute altera_dpram_16x32_inst NOOPT TRUE
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`else // !ETH_ALTERA_ALTSYNCRAM
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always @ (posedge clk)
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always @ (posedge clk)
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begin
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begin
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if(write & clear)
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if(write & clear)
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fifo[0] <=#Tp data_in;
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fifo[0] <=#Tp data_in;
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else
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else
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if(write & ~full)
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if(write & ~full)
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fifo[write_pointer] <=#Tp data_in;
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fifo[write_pointer] <=#Tp data_in;
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end
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end
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assign data_out = clear ? fifo[0] : fifo[read_pointer];
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`endif
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always @ (posedge clk)
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begin
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if(clear)
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data_out <=#Tp fifo[0];
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else
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data_out <=#Tp fifo[read_pointer];
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end
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`endif // !ETH_ALTERA_ALTSYNCRAM
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`endif // !ETH_FIFO_XILINX
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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