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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_macstatus.v] - Diff between revs 15 and 18

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Rev 15 Rev 18
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//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.1  2001/08/06 14:44:29  mohor
 
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
 
// Include files fixed to contain no path.
 
// File names and module names changed ta have a eth_ prologue in the name.
 
// File eth_timescale.v is used to define timescale
 
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
 
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
 
// and Mdo_OE. The bidirectional signal must be created on the top level. This
 
// is done due to the ASIC tools.
 
//
// Revision 1.1  2001/07/30 21:23:42  mohor
// Revision 1.1  2001/07/30 21:23:42  mohor
// Directory structure changed. Files checked and joind together.
// Directory structure changed. Files checked and joind together.
//
//
//
//
//
//
Line 118... Line 128...
    LatchedMRxErr <=#Tp 1'b0;
    LatchedMRxErr <=#Tp 1'b0;
  else
  else
  if(~MRxErr & MRxDV & RxStateIdle & ~Transmitting)
  if(~MRxErr & MRxDV & RxStateIdle & ~Transmitting)
    LatchedMRxErr <=#Tp 1'b0;
    LatchedMRxErr <=#Tp 1'b0;
  else
  else
  if(MRxErr & MRxDV & (RxStatePreamble | RxStateSFD | |RxStateData | RxStateIdle & ~Transmitting))
  if(MRxErr & MRxDV & (RxStatePreamble | RxStateSFD | (|RxStateData) | RxStateIdle & ~Transmitting))
    LatchedMRxErr <=#Tp 1'b1;
    LatchedMRxErr <=#Tp 1'b1;
end
end
 
 
 
 
// ReceivedPacketGood
// ReceivedPacketGood

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