| Line 428... |
Line 428... |
assign LatchByte1_d2 = InProgress & ~WriteOp & BitCounter == 7'h37;
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assign LatchByte1_d2 = InProgress & ~WriteOp & BitCounter == 7'h37;
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assign LatchByte0_d2 = InProgress & ~WriteOp & BitCounter == 7'h3F;
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assign LatchByte0_d2 = InProgress & ~WriteOp & BitCounter == 7'h3F;
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// Connecting the Clock Generator Module
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// Connecting the Clock Generator Module
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eth_clockgen clkgen(.Clk(Clk), .Reset(Reset), .Divider(Divider[7:0]), .MdcEn(MdcEn), .MdcEn_n(MdcEn_n), .Mdc(Mdc)
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eth_clockgen #(.Tp(Tp))
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clkgen(.Clk(Clk), .Reset(Reset), .Divider(Divider[7:0]), .MdcEn(MdcEn), .MdcEn_n(MdcEn_n), .Mdc(Mdc)
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);
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);
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// Connecting the Shift Register Module
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// Connecting the Shift Register Module
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eth_shiftreg shftrg(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .Mdi(Mdi), .Fiad(Fiad), .Rgad(Rgad),
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eth_shiftreg #(.Tp(Tp))
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shftrg(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .Mdi(Mdi), .Fiad(Fiad), .Rgad(Rgad),
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.CtrlData(CtrlData), .WriteOp(WriteOp), .ByteSelect(ByteSelect), .LatchByte(LatchByte),
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.CtrlData(CtrlData), .WriteOp(WriteOp), .ByteSelect(ByteSelect), .LatchByte(LatchByte),
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.ShiftedBit(ShiftedBit), .Prsd(Prsd), .LinkFail(LinkFail)
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.ShiftedBit(ShiftedBit), .Prsd(Prsd), .LinkFail(LinkFail)
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);
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);
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// Connecting the Output Control Module
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// Connecting the Output Control Module
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eth_outputcontrol outctrl(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .InProgress(InProgress),
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eth_outputcontrol #(.Tp(Tp))
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outctrl(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .InProgress(InProgress),
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.ShiftedBit(ShiftedBit), .BitCounter(BitCounter), .WriteOp(WriteOp), .NoPre(NoPre),
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.ShiftedBit(ShiftedBit), .BitCounter(BitCounter), .WriteOp(WriteOp), .NoPre(NoPre),
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.Mdo(Mdo), .MdoEn(MdoEn)
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.Mdo(Mdo), .MdoEn(MdoEn)
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);
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);
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endmodule
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endmodule
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