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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_receivecontrol.v] - Diff between revs 37 and 261

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Rev 37 Rev 261
Line 39... Line 39...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.3  2002/01/23 10:28:16  mohor
 
// Link in the header changed.
 
//
// Revision 1.2  2001/10/19 08:43:51  mohor
// Revision 1.2  2001/10/19 08:43:51  mohor
// eth_timescale.v changed to timescale.v This is done because of the
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
// simulation of the few cores in a one joined project.
//
//
// Revision 1.1  2001/08/06 14:44:29  mohor
// Revision 1.1  2001/08/06 14:44:29  mohor
Line 69... Line 72...
 
 
`include "timescale.v"
`include "timescale.v"
 
 
 
 
module eth_receivecontrol (MTxClk, MRxClk, TxReset, RxReset, RxData, RxValid, RxStartFrm,
module eth_receivecontrol (MTxClk, MRxClk, TxReset, RxReset, RxData, RxValid, RxStartFrm,
                           RxEndFrm, RxFlow, ReceiveEnd, MAC, PassAll, DlyCrcEn, TxDoneIn,
                           RxEndFrm, RxFlow, ReceiveEnd, MAC, DlyCrcEn, TxDoneIn,
                           TxAbortIn, TxStartFrmOut, ReceivedLengthOK, ReceivedPacketGood,
                           TxAbortIn, TxStartFrmOut, ReceivedLengthOK, ReceivedPacketGood,
                           TxUsedDataOutDetected, Pause, ReceivedPauseFrm
                           TxUsedDataOutDetected, Pause, ReceivedPauseFrm, AddressOK,
 
                           LoadRxStatus, SetPauseTimer
                          );
                          );
 
 
parameter Tp = 1;
parameter Tp = 1;
 
 
 
 
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input       RxStartFrm;
input       RxStartFrm;
input       RxEndFrm;
input       RxEndFrm;
input       RxFlow;
input       RxFlow;
input       ReceiveEnd;
input       ReceiveEnd;
input [47:0]MAC;
input [47:0]MAC;
input       PassAll;
 
input       DlyCrcEn;
input       DlyCrcEn;
input       TxDoneIn;
input       TxDoneIn;
input       TxAbortIn;
input       TxAbortIn;
input       TxStartFrmOut;
input       TxStartFrmOut;
input       ReceivedLengthOK;
input       ReceivedLengthOK;
input       ReceivedPacketGood;
input       ReceivedPacketGood;
input       TxUsedDataOutDetected;
input       TxUsedDataOutDetected;
 
input       LoadRxStatus;
 
 
output      Pause;
output      Pause;
output      ReceivedPauseFrm;
output      ReceivedPauseFrm;
 
output      AddressOK;
 
output      SetPauseTimer;
 
 
reg         Pause;
reg         Pause;
reg         AddressOK;                // Multicast or unicast address detected
reg         AddressOK;                // Multicast or unicast address detected
reg         TypeLengthOK;             // Type/Length field contains 0x8808
reg         TypeLengthOK;             // Type/Length field contains 0x8808
reg         DetectionWindow;          // Detection of the PAUSE frame is possible within this window
reg         DetectionWindow;          // Detection of the PAUSE frame is possible within this window
Line 134... Line 140...
wire        ByteCntEq14;              // ByteCnt = 14
wire        ByteCntEq14;              // ByteCnt = 14
wire        ByteCntEq15;              // ByteCnt = 15
wire        ByteCntEq15;              // ByteCnt = 15
wire        ByteCntEq16;              // ByteCnt = 16
wire        ByteCntEq16;              // ByteCnt = 16
wire        ByteCntEq17;              // ByteCnt = 17
wire        ByteCntEq17;              // ByteCnt = 17
wire        ByteCntEq18;              // ByteCnt = 18
wire        ByteCntEq18;              // ByteCnt = 18
wire        SetPauseTimer;            // 
 
wire        DecrementPauseTimer;      // 
wire        DecrementPauseTimer;      // 
wire        PauseTimerEq0;            // 
wire        PauseTimerEq0;            // 
wire        ResetSlotTimer;           // 
wire        ResetSlotTimer;           // 
wire        IncrementSlotTimer;       // 
wire        IncrementSlotTimer;       // 
wire        SlotFinished;             // 
wire        SlotFinished;             // 
Line 269... Line 274...
always @ (posedge MRxClk or posedge RxReset )
always @ (posedge MRxClk or posedge RxReset )
begin
begin
  if(RxReset)
  if(RxReset)
    LatchedTimerValue[15:0] <= #Tp 16'h0;
    LatchedTimerValue[15:0] <= #Tp 16'h0;
  else
  else
  if(~PassAll & DetectionWindow &  ReceivedPauseFrmWAddr &  ByteCntEq18)
  if(DetectionWindow &  ReceivedPauseFrmWAddr &  ByteCntEq18)
    LatchedTimerValue[15:0] <= #Tp AssembledTimerValue[15:0];
    LatchedTimerValue[15:0] <= #Tp AssembledTimerValue[15:0];
  else
  else
  if(ReceiveEnd)
  if(ReceiveEnd)
    LatchedTimerValue[15:0] <= #Tp 16'h0;
    LatchedTimerValue[15:0] <= #Tp 16'h0;
end
end
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    ReceivedPauseFrm <=#Tp 1'b0;
    ReceivedPauseFrm <=#Tp 1'b0;
  else
  else
  if(ByteCntEq16 & TypeLengthOK & OpCodeOK)
  if(ByteCntEq16 & TypeLengthOK & OpCodeOK)
    ReceivedPauseFrm <=#Tp 1'b1;
    ReceivedPauseFrm <=#Tp 1'b1;
  else
  else
  if(ReceiveEnd)
  if(RxStartFrm)
    ReceivedPauseFrm <=#Tp 1'b0;
    ReceivedPauseFrm <=#Tp 1'b0;
end
end
 
 
 
 
endmodule
endmodule

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