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https://opencores.org/ocsvn/ethmac/ethmac/trunk
[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_receivecontrol.v] - Diff between revs 352 and 353
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Rev 352 |
Rev 353 |
Line 297... |
Line 297... |
else
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else
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if(RxValid & RxEndFrm)
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if(RxValid & RxEndFrm)
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DlyCrcCnt <= 3'h0;
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DlyCrcCnt <= 3'h0;
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else
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else
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if(RxValid & ~RxEndFrm & ~DlyCrcCnt[2])
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if(RxValid & ~RxEndFrm & ~DlyCrcCnt[2])
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DlyCrcCnt <= DlyCrcCnt + 1'b1;
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DlyCrcCnt <= DlyCrcCnt + 3'd1;
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end
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end
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assign ResetByteCnt = RxEndFrm;
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assign ResetByteCnt = RxEndFrm;
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assign IncrementByteCnt = RxValid & DetectionWindow & ~ByteCntEq18 & (~DlyCrcEn | DlyCrcEn & DlyCrcCnt[2]);
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assign IncrementByteCnt = RxValid & DetectionWindow & ~ByteCntEq18 & (~DlyCrcEn | DlyCrcEn & DlyCrcCnt[2]);
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Line 315... |
Line 315... |
else
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else
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if(ResetByteCnt)
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if(ResetByteCnt)
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ByteCnt[4:0] <= 5'h0;
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ByteCnt[4:0] <= 5'h0;
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else
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else
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if(IncrementByteCnt)
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if(IncrementByteCnt)
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ByteCnt[4:0] <= ByteCnt[4:0] + 1'b1;
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ByteCnt[4:0] <= ByteCnt[4:0] + 5'd1;
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end
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end
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assign ByteCntEq0 = RxValid & ByteCnt[4:0] == 5'h0;
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assign ByteCntEq0 = RxValid & ByteCnt[4:0] == 5'h0;
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assign ByteCntEq1 = RxValid & ByteCnt[4:0] == 5'h1;
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assign ByteCntEq1 = RxValid & ByteCnt[4:0] == 5'h1;
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Line 348... |
Line 348... |
else
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else
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if(SetPauseTimer)
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if(SetPauseTimer)
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PauseTimer[15:0] <= LatchedTimerValue[15:0];
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PauseTimer[15:0] <= LatchedTimerValue[15:0];
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else
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else
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if(DecrementPauseTimer)
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if(DecrementPauseTimer)
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PauseTimer[15:0] <= PauseTimer[15:0] - 1'b1;
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PauseTimer[15:0] <= PauseTimer[15:0] - 16'd1;
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end
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end
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assign PauseTimerEq0 = ~(|PauseTimer[15:0]);
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assign PauseTimerEq0 = ~(|PauseTimer[15:0]);
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Line 409... |
Line 409... |
else
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else
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if(ResetSlotTimer)
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if(ResetSlotTimer)
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SlotTimer[5:0] <= 6'h0;
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SlotTimer[5:0] <= 6'h0;
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else
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else
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if(IncrementSlotTimer)
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if(IncrementSlotTimer)
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SlotTimer[5:0] <= SlotTimer[5:0] + 1'b1;
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SlotTimer[5:0] <= SlotTimer[5:0] + 6'd1;
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end
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end
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assign SlotFinished = &SlotTimer[5:0] & IncrementSlotTimer; // Slot is 512 bits (64 bytes)
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assign SlotFinished = &SlotTimer[5:0] & IncrementSlotTimer; // Slot is 512 bits (64 bytes)
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