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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_registers.v] - Diff between revs 321 and 333

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//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.28  2004/04/26 15:26:23  igorm
 
// - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
 
//   previous update of the core.
 
// - TxBDAddress is set to 0 after the TX is enabled in the MODER register.
 
// - RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER
 
//   register. (thanks to Mathias and Torbjorn)
 
// - Multicast reception was fixed. Thanks to Ulrich Gries
 
//
// Revision 1.27  2004/04/26 11:42:17  igorm
// Revision 1.27  2004/04/26 11:42:17  igorm
// TX_BD_NUM_Wr error fixed. Error was entered with the last check-in.
// TX_BD_NUM_Wr error fixed. Error was entered with the last check-in.
//
//
// Revision 1.26  2003/11/12 18:24:59  tadejm
// Revision 1.26  2003/11/12 18:24:59  tadejm
// WISHBONE slave changed and tested from only 32-bit accesss to byte access.
// WISHBONE slave changed and tested from only 32-bit accesss to byte access.
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wire [3:0] MAC_ADDR0_Wr;
wire [3:0] MAC_ADDR0_Wr;
wire [1:0] MAC_ADDR1_Wr;
wire [1:0] MAC_ADDR1_Wr;
wire [3:0] HASH0_Wr;
wire [3:0] HASH0_Wr;
wire [3:0] HASH1_Wr;
wire [3:0] HASH1_Wr;
wire [2:0] TXCTRL_Wr;
wire [2:0] TXCTRL_Wr;
wire [1:0] RXCTRL_Wr;
 
wire [0:0] TX_BD_NUM_Wr;
wire [0:0] TX_BD_NUM_Wr;
 
 
assign MODER_Wr[0]       = Write[0]  & MODER_Sel;
assign MODER_Wr[0]       = Write[0]  & MODER_Sel;
assign MODER_Wr[1]       = Write[1]  & MODER_Sel;
assign MODER_Wr[1]       = Write[1]  & MODER_Sel;
assign MODER_Wr[2]       = Write[2]  & MODER_Sel;
assign MODER_Wr[2]       = Write[2]  & MODER_Sel;
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assign HASH1_Wr[2]       = Write[2]  & HASH1_Sel;
assign HASH1_Wr[2]       = Write[2]  & HASH1_Sel;
assign HASH1_Wr[3]       = Write[3]  & HASH1_Sel;
assign HASH1_Wr[3]       = Write[3]  & HASH1_Sel;
assign TXCTRL_Wr[0]      = Write[0]  & TXCTRL_Sel;
assign TXCTRL_Wr[0]      = Write[0]  & TXCTRL_Sel;
assign TXCTRL_Wr[1]      = Write[1]  & TXCTRL_Sel;
assign TXCTRL_Wr[1]      = Write[1]  & TXCTRL_Sel;
assign TXCTRL_Wr[2]      = Write[2]  & TXCTRL_Sel;
assign TXCTRL_Wr[2]      = Write[2]  & TXCTRL_Sel;
assign RXCTRL_Wr[0]      = Write[0]  & RXCTRL_Sel;
 
assign RXCTRL_Wr[1]      = Write[1]  & RXCTRL_Sel;
 
assign TX_BD_NUM_Wr[0]   = Write[0]  & TX_BD_NUM_Sel & (DataIn<='h80);
assign TX_BD_NUM_Wr[0]   = Write[0]  & TX_BD_NUM_Sel & (DataIn<='h80);
 
 
 
 
 
 
wire [31:0] MODEROut;
wire [31:0] MODEROut;
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wire [31:0] MAC_ADDR1Out;
wire [31:0] MAC_ADDR1Out;
wire [31:0] TX_BD_NUMOut;
wire [31:0] TX_BD_NUMOut;
wire [31:0] HASH0Out;
wire [31:0] HASH0Out;
wire [31:0] HASH1Out;
wire [31:0] HASH1Out;
wire [31:0] TXCTRLOut;
wire [31:0] TXCTRLOut;
wire [31:0] RXCTRLOut;
 
 
 
// MODER Register
// MODER Register
eth_register #(`ETH_MODER_WIDTH_0, `ETH_MODER_DEF_0)        MODER_0
eth_register #(`ETH_MODER_WIDTH_0, `ETH_MODER_DEF_0)        MODER_0
  (
  (
   .DataIn    (DataIn[`ETH_MODER_WIDTH_0 - 1:0]),
   .DataIn    (DataIn[`ETH_MODER_WIDTH_0 - 1:0]),
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   .Reset     (Reset),
   .Reset     (Reset),
   .SyncReset (RstTxPauseRq)
   .SyncReset (RstTxPauseRq)
  );
  );
assign TXCTRLOut[31:`ETH_TX_CTRL_WIDTH_2 + 16] = 0;
assign TXCTRLOut[31:`ETH_TX_CTRL_WIDTH_2 + 16] = 0;
 
 
// RXCTRL Register
 
eth_register #(`ETH_RX_CTRL_WIDTH_0, `ETH_RX_CTRL_DEF_0)      RXCTRL_0
 
  (
 
   .DataIn    (DataIn[`ETH_RX_CTRL_WIDTH_0 - 1:0]),
 
   .DataOut   (RXCTRLOut[`ETH_RX_CTRL_WIDTH_0 - 1:0]),
 
   .Write     (RXCTRL_Wr[0]),
 
   .Clk       (Clk),
 
   .Reset     (Reset),
 
   .SyncReset (1'b0)
 
  );
 
eth_register #(`ETH_RX_CTRL_WIDTH_1, `ETH_RX_CTRL_DEF_1)      RXCTRL_1
 
  (
 
   .DataIn    (DataIn[`ETH_RX_CTRL_WIDTH_1 + 7:8]),
 
   .DataOut   (RXCTRLOut[`ETH_RX_CTRL_WIDTH_1 + 7:8]),
 
   .Write     (RXCTRL_Wr[1]),
 
   .Clk       (Clk),
 
   .Reset     (Reset),
 
   .SyncReset (1'b0)
 
  );
 
assign RXCTRLOut[31:`ETH_RX_CTRL_WIDTH_1 + 8] = 0;
 
 
 
 
 
// Reading data from registers
// Reading data from registers
always @ (Address       or Read           or MODEROut       or INT_SOURCEOut  or
always @ (Address       or Read           or MODEROut       or INT_SOURCEOut  or
          INT_MASKOut   or IPGTOut        or IPGR1Out       or IPGR2Out       or
          INT_MASKOut   or IPGTOut        or IPGR1Out       or IPGR2Out       or
          PACKETLENOut  or COLLCONFOut    or CTRLMODEROut   or MIIMODEROut    or
          PACKETLENOut  or COLLCONFOut    or CTRLMODEROut   or MIIMODEROut    or
          MIICOMMANDOut or MIIADDRESSOut  or MIITX_DATAOut  or MIIRX_DATAOut  or
          MIICOMMANDOut or MIIADDRESSOut  or MIITX_DATAOut  or MIIRX_DATAOut  or
          MIISTATUSOut  or MAC_ADDR0Out   or MAC_ADDR1Out   or TX_BD_NUMOut   or
          MIISTATUSOut  or MAC_ADDR0Out   or MAC_ADDR1Out   or TX_BD_NUMOut   or
          HASH0Out      or HASH1Out       or TXCTRLOut      or RXCTRLOut
          HASH0Out      or HASH1Out       or TXCTRLOut
         )
         )
begin
begin
  if(Read)  // read
  if(Read)  // read
    begin
    begin
      case(Address)
      case(Address)
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        `ETH_MAC_ADDR1_ADR    :  DataOut<=MAC_ADDR1Out;
        `ETH_MAC_ADDR1_ADR    :  DataOut<=MAC_ADDR1Out;
        `ETH_TX_BD_NUM_ADR    :  DataOut<=TX_BD_NUMOut;
        `ETH_TX_BD_NUM_ADR    :  DataOut<=TX_BD_NUMOut;
        `ETH_HASH0_ADR        :  DataOut<=HASH0Out;
        `ETH_HASH0_ADR        :  DataOut<=HASH0Out;
        `ETH_HASH1_ADR        :  DataOut<=HASH1Out;
        `ETH_HASH1_ADR        :  DataOut<=HASH1Out;
        `ETH_TX_CTRL_ADR      :  DataOut<=TXCTRLOut;
        `ETH_TX_CTRL_ADR      :  DataOut<=TXCTRLOut;
        `ETH_RX_CTRL_ADR      :  DataOut<=RXCTRLOut;
 
 
 
        default:             DataOut<=32'h0;
        default:             DataOut<=32'h0;
      endcase
      endcase
    end
    end
  else
  else

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