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//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
////  eth_rxaddrcheck.v                                           ////
////  eth_rxaddrcheck.v                                           ////
////                                                              ////
////                                                              ////
////  This file is part of the Ethernet IP core project           ////
////  This file is part of the Ethernet IP core project           ////
////  http://www.opencores.org/cores/ethmac/                      ////
////  http://www.opencores.org/project,ethmac/                    ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////  Author(s):                                                  ////
////      - Bill Dittenhofer (billditt@aol.com)                   ////
////      - Bill Dittenhofer (billditt@aol.com)                   ////
 
////      - Olof Kindgren    (olof@opencores.org)                 ////
////                                                              ////
////                                                              ////
////  All additional information is avaliable in the Readme.txt   ////
////  All additional information is avaliable in the Readme.txt   ////
////  file.                                                       ////
////  file.                                                       ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
//// Copyright (C) 2001 Authors                                   ////
//// Copyright (C) 2011 Authors                                   ////
////                                                              ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
//// the original copyright notice and the associated disclaimer. ////
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//// Public License along with this source; if not, download it   ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
 
// 2011-07-06 Olof Kindgren <olof@opencores.org>
 
// Reset AdressMiss when a new frame arrives. Otherwise it will report
 
// the last value when a frame is less than seven bytes
 
//
// CVS Revision History
// CVS Revision History
//
//
 
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
// Revision 1.8  2002/11/19 17:34:52  mohor
//
 
//  // Revision 1.8  2002/11/19 17:34:52  mohor
// AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
// AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
// that a frame was received because of the promiscous mode.
// that a frame was received because of the promiscous mode.
//
//
// Revision 1.7  2002/09/04 18:41:06  mohor
// Revision 1.7  2002/09/04 18:41:06  mohor
// Bug when last byte of destination address was not checked fixed.
// Bug when last byte of destination address was not checked fixed.
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`include "timescale.v"
`include "timescale.v"
 
 
 
 
module eth_rxaddrcheck(MRxClk,  Reset, RxData, Broadcast ,r_Bro ,r_Pro,
module eth_rxaddrcheck(MRxClk,  Reset, RxData, Broadcast ,r_Bro ,r_Pro,
                       ByteCntEq2, ByteCntEq3, ByteCntEq4, ByteCntEq5,
                       ByteCntEq2, ByteCntEq3, ByteCntEq4, ByteCntEq5,
                       ByteCntEq6, ByteCntEq7, HASH0, HASH1,
                       ByteCntEq6, ByteCntEq7, HASH0, HASH1, ByteCntEq0,
                       CrcHash,    CrcHashGood, StateData, RxEndFrm,
                       CrcHash,    CrcHashGood, StateData, RxEndFrm,
                       Multicast, MAC, RxAbort, AddressMiss, PassAll,
                       Multicast, MAC, RxAbort, AddressMiss, PassAll,
                       ControlFrmAddressOK
                       ControlFrmAddressOK
                      );
                      );
 
 
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  input        Reset;
  input        Reset;
  input [7:0]  RxData;
  input [7:0]  RxData;
  input        Broadcast;
  input        Broadcast;
  input        r_Bro;
  input        r_Bro;
  input        r_Pro;
  input        r_Pro;
 
  input        ByteCntEq0;
  input        ByteCntEq2;
  input        ByteCntEq2;
  input        ByteCntEq3;
  input        ByteCntEq3;
  input        ByteCntEq4;
  input        ByteCntEq4;
  input        ByteCntEq5;
  input        ByteCntEq5;
  input        ByteCntEq6;
  input        ByteCntEq6;
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// This ff holds the "Address Miss" information that is written to the RX BD status.
// This ff holds the "Address Miss" information that is written to the RX BD status.
always @ (posedge MRxClk or posedge Reset)
always @ (posedge MRxClk or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    AddressMiss <= #Tp 1'b0;
    AddressMiss <= #Tp 1'b0;
 
  else if(ByteCntEq0)
 
    AddressMiss <= #Tp 1'b0;
  else if(ByteCntEq7 & RxCheckEn)
  else if(ByteCntEq7 & RxCheckEn)
    AddressMiss <= #Tp (~(UnicastOK | BroadcastOK | MulticastOK | (PassAll & ControlFrmAddressOK)));
    AddressMiss <= #Tp (~(UnicastOK | BroadcastOK | MulticastOK | (PassAll & ControlFrmAddressOK)));
end
end
 
 
 
 

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