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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_rxaddrcheck.v] - Diff between revs 341 and 352

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Rev 341 Rev 352
Line 80... Line 80...
                       CrcHash,    CrcHashGood, StateData, RxEndFrm,
                       CrcHash,    CrcHashGood, StateData, RxEndFrm,
                       Multicast, MAC, RxAbort, AddressMiss, PassAll,
                       Multicast, MAC, RxAbort, AddressMiss, PassAll,
                       ControlFrmAddressOK
                       ControlFrmAddressOK
                      );
                      );
 
 
parameter Tp = 1;
 
 
 
  input        MRxClk;
  input        MRxClk;
  input        Reset;
  input        Reset;
  input [7:0]  RxData;
  input [7:0]  RxData;
  input        Broadcast;
  input        Broadcast;
Line 136... Line 135...
 // RxAbort clears after one cycle
 // RxAbort clears after one cycle
 
 
always @ (posedge MRxClk or posedge Reset)
always @ (posedge MRxClk or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    RxAbort <= #Tp 1'b0;
    RxAbort <=  1'b0;
  else if(RxAddressInvalid & ByteCntEq7 & RxCheckEn)
  else if(RxAddressInvalid & ByteCntEq7 & RxCheckEn)
    RxAbort <= #Tp 1'b1;
    RxAbort <=  1'b1;
  else
  else
    RxAbort <= #Tp 1'b0;
    RxAbort <=  1'b0;
end
end
 
 
 
 
// This ff holds the "Address Miss" information that is written to the RX BD status.
// This ff holds the "Address Miss" information that is written to the RX BD status.
always @ (posedge MRxClk or posedge Reset)
always @ (posedge MRxClk or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    AddressMiss <= #Tp 1'b0;
    AddressMiss <=  1'b0;
  else if(ByteCntEq0)
  else if(ByteCntEq0)
    AddressMiss <= #Tp 1'b0;
    AddressMiss <=  1'b0;
  else if(ByteCntEq7 & RxCheckEn)
  else if(ByteCntEq7 & RxCheckEn)
    AddressMiss <= #Tp (~(UnicastOK | BroadcastOK | MulticastOK | (PassAll & ControlFrmAddressOK)));
    AddressMiss <=  (~(UnicastOK | BroadcastOK | MulticastOK | (PassAll & ControlFrmAddressOK)));
end
end
 
 
 
 
// Hash Address Check, Multicast
// Hash Address Check, Multicast
always @ (posedge MRxClk or posedge Reset)
always @ (posedge MRxClk or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    MulticastOK <= #Tp 1'b0;
    MulticastOK <=  1'b0;
  else if(RxEndFrm | RxAbort)
  else if(RxEndFrm | RxAbort)
    MulticastOK <= #Tp 1'b0;
    MulticastOK <=  1'b0;
  else if(CrcHashGood & Multicast)
  else if(CrcHashGood & Multicast)
    MulticastOK <= #Tp HashBit;
    MulticastOK <=  HashBit;
end
end
 
 
 
 
// Address Detection (unicast)
// Address Detection (unicast)
// start with ByteCntEq2 due to delay of addres from RxData
// start with ByteCntEq2 due to delay of addres from RxData
always @ (posedge MRxClk or posedge Reset)
always @ (posedge MRxClk or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    UnicastOK <= #Tp 1'b0;
    UnicastOK <=  1'b0;
  else
  else
  if(RxCheckEn & ByteCntEq2)
  if(RxCheckEn & ByteCntEq2)
    UnicastOK <= #Tp   RxData[7:0] == MAC[47:40];
    UnicastOK <=    RxData[7:0] == MAC[47:40];
  else
  else
  if(RxCheckEn & ByteCntEq3)
  if(RxCheckEn & ByteCntEq3)
    UnicastOK <= #Tp ( RxData[7:0] == MAC[39:32]) & UnicastOK;
    UnicastOK <=  ( RxData[7:0] == MAC[39:32]) & UnicastOK;
  else
  else
  if(RxCheckEn & ByteCntEq4)
  if(RxCheckEn & ByteCntEq4)
    UnicastOK <= #Tp ( RxData[7:0] == MAC[31:24]) & UnicastOK;
    UnicastOK <=  ( RxData[7:0] == MAC[31:24]) & UnicastOK;
  else
  else
  if(RxCheckEn & ByteCntEq5)
  if(RxCheckEn & ByteCntEq5)
    UnicastOK <= #Tp ( RxData[7:0] == MAC[23:16]) & UnicastOK;
    UnicastOK <=  ( RxData[7:0] == MAC[23:16]) & UnicastOK;
  else
  else
  if(RxCheckEn & ByteCntEq6)
  if(RxCheckEn & ByteCntEq6)
    UnicastOK <= #Tp ( RxData[7:0] == MAC[15:8])  & UnicastOK;
    UnicastOK <=  ( RxData[7:0] == MAC[15:8])  & UnicastOK;
  else
  else
  if(RxCheckEn & ByteCntEq7)
  if(RxCheckEn & ByteCntEq7)
    UnicastOK <= #Tp ( RxData[7:0] == MAC[7:0])   & UnicastOK;
    UnicastOK <=  ( RxData[7:0] == MAC[7:0])   & UnicastOK;
  else
  else
  if(RxEndFrm | RxAbort)
  if(RxEndFrm | RxAbort)
    UnicastOK <= #Tp 1'b0;
    UnicastOK <=  1'b0;
end
end
 
 
assign IntHash = (CrcHash[5])? HASH1 : HASH0;
assign IntHash = (CrcHash[5])? HASH1 : HASH0;
 
 
always@(CrcHash or IntHash)
always@(CrcHash or IntHash)

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