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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_rxcounters.v] - Diff between revs 346 and 352

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Rev 346 Rev 352
Line 87... Line 87...
                       MRxDEqD, DlyCrcEn, DlyCrcCnt, Transmitting, MaxFL, r_IFG, HugEn, IFGCounterEq24,
                       MRxDEqD, DlyCrcEn, DlyCrcCnt, Transmitting, MaxFL, r_IFG, HugEn, IFGCounterEq24,
                       ByteCntEq0, ByteCntEq1, ByteCntEq2,ByteCntEq3,ByteCntEq4,ByteCntEq5, ByteCntEq6,
                       ByteCntEq0, ByteCntEq1, ByteCntEq2,ByteCntEq3,ByteCntEq4,ByteCntEq5, ByteCntEq6,
                       ByteCntEq7, ByteCntGreat2, ByteCntSmall7, ByteCntMaxFrame, ByteCntOut
                       ByteCntEq7, ByteCntGreat2, ByteCntSmall7, ByteCntMaxFrame, ByteCntOut
                      );
                      );
 
 
parameter Tp = 1;
 
 
 
input         MRxClk;
input         MRxClk;
input         Reset;
input         Reset;
input         MRxDV;
input         MRxDV;
input         StateSFD;
input         StateSFD;
input [1:0]   StateData;
input [1:0]   StateData;
Line 144... Line 142...
 
 
 
 
always @ (posedge MRxClk or posedge Reset)
always @ (posedge MRxClk or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    ByteCnt[15:0] <= #Tp 16'h0;
    ByteCnt[15:0] <=  16'h0;
  else
  else
    begin
    begin
      if(ResetByteCounter)
      if(ResetByteCounter)
        ByteCnt[15:0] <= #Tp 16'h0;
        ByteCnt[15:0] <=  16'h0;
      else
      else
      if(IncrementByteCounter)
      if(IncrementByteCounter)
        ByteCnt[15:0] <= #Tp ByteCnt[15:0] + 1'b1;
        ByteCnt[15:0] <=  ByteCnt[15:0] + 1'b1;
     end
     end
end
end
 
 
assign ByteCntDelayed = ByteCnt + 3'h4;
assign ByteCntDelayed = ByteCnt + 3'h4;
assign ByteCntOut = DlyCrcEn? ByteCntDelayed : ByteCnt;
assign ByteCntOut = DlyCrcEn? ByteCntDelayed : ByteCnt;
Line 179... Line 177...
assign IncrementIFGCounter = ~ResetIFGCounter & (StateDrop | StateIdle | StatePreamble | StateSFD) & ~IFGCounterEq24;
assign IncrementIFGCounter = ~ResetIFGCounter & (StateDrop | StateIdle | StatePreamble | StateSFD) & ~IFGCounterEq24;
 
 
always @ (posedge MRxClk or posedge Reset)
always @ (posedge MRxClk or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    IFGCounter[4:0] <= #Tp 5'h0;
    IFGCounter[4:0] <=  5'h0;
  else
  else
    begin
    begin
      if(ResetIFGCounter)
      if(ResetIFGCounter)
        IFGCounter[4:0] <= #Tp 5'h0;
        IFGCounter[4:0] <=  5'h0;
      else
      else
      if(IncrementIFGCounter)
      if(IncrementIFGCounter)
        IFGCounter[4:0] <= #Tp IFGCounter[4:0] + 1'b1;
        IFGCounter[4:0] <=  IFGCounter[4:0] + 1'b1;
    end
    end
end
end
 
 
 
 
 
 
Line 198... Line 196...
 
 
 
 
always @ (posedge MRxClk or posedge Reset)
always @ (posedge MRxClk or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    DlyCrcCnt[3:0] <= #Tp 4'h0;
    DlyCrcCnt[3:0] <=  4'h0;
  else
  else
    begin
    begin
      if(DlyCrcCnt[3:0] == 4'h9)
      if(DlyCrcCnt[3:0] == 4'h9)
        DlyCrcCnt[3:0] <= #Tp 4'h0;
        DlyCrcCnt[3:0] <=  4'h0;
      else
      else
      if(DlyCrcEn & StateSFD)
      if(DlyCrcEn & StateSFD)
        DlyCrcCnt[3:0] <= #Tp 4'h1;
        DlyCrcCnt[3:0] <=  4'h1;
      else
      else
      if(DlyCrcEn & (|DlyCrcCnt[3:0]))
      if(DlyCrcEn & (|DlyCrcCnt[3:0]))
        DlyCrcCnt[3:0] <= #Tp DlyCrcCnt[3:0] + 1'b1;
        DlyCrcCnt[3:0] <=  DlyCrcCnt[3:0] + 1'b1;
    end
    end
end
end
 
 
 
 
endmodule
endmodule

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