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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_rxethmac.v] - Diff between revs 65 and 250

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//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.8  2002/02/16 07:15:27  mohor
 
// Testbench fixed, code simplified, unused signals removed.
 
//
// Revision 1.7  2002/02/15 13:44:28  mohor
// Revision 1.7  2002/02/15 13:44:28  mohor
// RxAbort is an output. No need to have is declared as wire.
// RxAbort is an output. No need to have is declared as wire.
//
//
// Revision 1.6  2002/02/15 11:17:48  mohor
// Revision 1.6  2002/02/15 11:17:48  mohor
// File format changed.
// File format changed.
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module eth_rxethmac (MRxClk, MRxDV, MRxD, Reset, Transmitting, MaxFL, r_IFG, HugEn, DlyCrcEn,
module eth_rxethmac (MRxClk, MRxDV, MRxD, Reset, Transmitting, MaxFL, r_IFG, HugEn, DlyCrcEn,
                     RxData, RxValid, RxStartFrm, RxEndFrm, ByteCnt, ByteCntEq0, ByteCntGreat2,
                     RxData, RxValid, RxStartFrm, RxEndFrm, ByteCnt, ByteCntEq0, ByteCntGreat2,
                     ByteCntMaxFrame, CrcError, StateIdle, StatePreamble, StateSFD, StateData,
                     ByteCntMaxFrame, CrcError, StateIdle, StatePreamble, StateSFD, StateData,
                     MAC, r_Pro, r_Bro,r_HASH0, r_HASH1, RxAbort
                     MAC, r_Pro, r_Bro,r_HASH0, r_HASH1, RxAbort, AddressMiss
                    );
                    );
 
 
parameter Tp = 1;
parameter Tp = 1;
 
 
 
 
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output        StateIdle;
output        StateIdle;
output        StatePreamble;
output        StatePreamble;
output        StateSFD;
output        StateSFD;
output  [1:0] StateData;
output  [1:0] StateData;
output        RxAbort;
output        RxAbort;
 
output        AddressMiss;
 
 
reg     [7:0] RxData;
reg     [7:0] RxData;
reg           RxValid;
reg           RxValid;
reg           RxStartFrm;
reg           RxStartFrm;
reg           RxEndFrm;
reg           RxEndFrm;
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               .ByteCntEq6(ByteCntEq6), .ByteCntEq7(ByteCntEq7), .ByteCntEq2(ByteCntEq2),
               .ByteCntEq6(ByteCntEq6), .ByteCntEq7(ByteCntEq7), .ByteCntEq2(ByteCntEq2),
               .ByteCntEq3(ByteCntEq3), .ByteCntEq4(ByteCntEq4), .ByteCntEq5(ByteCntEq5),
               .ByteCntEq3(ByteCntEq3), .ByteCntEq4(ByteCntEq4), .ByteCntEq5(ByteCntEq5),
               .HASH0(r_HASH0),         .HASH1(r_HASH1),
               .HASH0(r_HASH0),         .HASH1(r_HASH1),
               .CrcHash(CrcHash[5:0]),  .CrcHashGood(CrcHashGood),.StateData(StateData),
               .CrcHash(CrcHash[5:0]),  .CrcHashGood(CrcHashGood),.StateData(StateData),
               .Multicast(Multicast),   .MAC(MAC),               .RxAbort(RxAbort),
               .Multicast(Multicast),   .MAC(MAC),               .RxAbort(RxAbort),
               .RxEndFrm(RxEndFrm)
               .RxEndFrm(RxEndFrm),     .AddressMiss(AddressMiss)
              );
              );
 
 
 
 
assign Enable_Crc = MRxDV & (|StateData & ~ByteCntMaxFrame);
assign Enable_Crc = MRxDV & (|StateData & ~ByteCntMaxFrame);
assign Initialize_Crc = StateSFD | DlyCrcEn & (|DlyCrcCnt[3:0]) & DlyCrcCnt[3:0] < 4'h9;
assign Initialize_Crc = StateSFD | DlyCrcEn & (|DlyCrcCnt[3:0]) & DlyCrcCnt[3:0] < 4'h9;

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