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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_rxethmac.v] - Diff between revs 250 and 261

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//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.9  2002/11/19 17:35:35  mohor
 
// AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
 
// that a frame was received because of the promiscous mode.
 
//
// Revision 1.8  2002/02/16 07:15:27  mohor
// Revision 1.8  2002/02/16 07:15:27  mohor
// Testbench fixed, code simplified, unused signals removed.
// Testbench fixed, code simplified, unused signals removed.
//
//
// Revision 1.7  2002/02/15 13:44:28  mohor
// Revision 1.7  2002/02/15 13:44:28  mohor
// RxAbort is an output. No need to have is declared as wire.
// RxAbort is an output. No need to have is declared as wire.
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module eth_rxethmac (MRxClk, MRxDV, MRxD, Reset, Transmitting, MaxFL, r_IFG, HugEn, DlyCrcEn,
module eth_rxethmac (MRxClk, MRxDV, MRxD, Reset, Transmitting, MaxFL, r_IFG, HugEn, DlyCrcEn,
                     RxData, RxValid, RxStartFrm, RxEndFrm, ByteCnt, ByteCntEq0, ByteCntGreat2,
                     RxData, RxValid, RxStartFrm, RxEndFrm, ByteCnt, ByteCntEq0, ByteCntGreat2,
                     ByteCntMaxFrame, CrcError, StateIdle, StatePreamble, StateSFD, StateData,
                     ByteCntMaxFrame, CrcError, StateIdle, StatePreamble, StateSFD, StateData,
                     MAC, r_Pro, r_Bro,r_HASH0, r_HASH1, RxAbort, AddressMiss
                     MAC, r_Pro, r_Bro,r_HASH0, r_HASH1, RxAbort, AddressMiss, PassAll, ControlFrmAddressOK
                    );
                    );
 
 
parameter Tp = 1;
parameter Tp = 1;
 
 
 
 
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input  [47:0] MAC;     //  Station Address  
input  [47:0] MAC;     //  Station Address  
input         r_Bro;   //  broadcast disable
input         r_Bro;   //  broadcast disable
input         r_Pro;   //  promiscuous enable 
input         r_Pro;   //  promiscuous enable 
input [31:0]  r_HASH0; //  lower 4 bytes Hash Table
input [31:0]  r_HASH0; //  lower 4 bytes Hash Table
input [31:0]  r_HASH1; //  upper 4 bytes Hash Table
input [31:0]  r_HASH1; //  upper 4 bytes Hash Table
 
input         PassAll;
 
input         ControlFrmAddressOK;
 
 
output  [7:0] RxData;
output  [7:0] RxData;
output        RxValid;
output        RxValid;
output        RxStartFrm;
output        RxStartFrm;
output        RxEndFrm;
output        RxEndFrm;
output [15:0] ByteCnt;
output [15:0] ByteCnt;
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               .ByteCntEq6(ByteCntEq6), .ByteCntEq7(ByteCntEq7), .ByteCntEq2(ByteCntEq2),
               .ByteCntEq6(ByteCntEq6), .ByteCntEq7(ByteCntEq7), .ByteCntEq2(ByteCntEq2),
               .ByteCntEq3(ByteCntEq3), .ByteCntEq4(ByteCntEq4), .ByteCntEq5(ByteCntEq5),
               .ByteCntEq3(ByteCntEq3), .ByteCntEq4(ByteCntEq4), .ByteCntEq5(ByteCntEq5),
               .HASH0(r_HASH0),         .HASH1(r_HASH1),
               .HASH0(r_HASH0),         .HASH1(r_HASH1),
               .CrcHash(CrcHash[5:0]),  .CrcHashGood(CrcHashGood),.StateData(StateData),
               .CrcHash(CrcHash[5:0]),  .CrcHashGood(CrcHashGood),.StateData(StateData),
               .Multicast(Multicast),   .MAC(MAC),               .RxAbort(RxAbort),
               .Multicast(Multicast),   .MAC(MAC),               .RxAbort(RxAbort),
               .RxEndFrm(RxEndFrm),     .AddressMiss(AddressMiss)
               .RxEndFrm(RxEndFrm),     .AddressMiss(AddressMiss),  .PassAll(PassAll),
 
               .ControlFrmAddressOK(ControlFrmAddressOK)
              );
              );
 
 
 
 
assign Enable_Crc = MRxDV & (|StateData & ~ByteCntMaxFrame);
assign Enable_Crc = MRxDV & (|StateData & ~ByteCntMaxFrame);
assign Initialize_Crc = StateSFD | DlyCrcEn & (|DlyCrcCnt[3:0]) & DlyCrcCnt[3:0] < 4'h9;
assign Initialize_Crc = StateSFD | DlyCrcEn & (|DlyCrcCnt[3:0]) & DlyCrcCnt[3:0] < 4'h9;

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