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Line 41... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1 2001/08/06 14:44:29 mohor
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// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
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// Include files fixed to contain no path.
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// File names and module names changed ta have a eth_ prologue in the name.
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// File eth_timescale.v is used to define timescale
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// All pin names on the top module are changed to contain _I, _O or _OE at the end.
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// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
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// and Mdo_OE. The bidirectional signal must be created on the top level. This
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// is done due to the ASIC tools.
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//
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// Revision 1.1 2001/07/30 21:23:42 mohor
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// Revision 1.1 2001/07/30 21:23:42 mohor
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// Directory structure changed. Files checked and joind together.
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// Directory structure changed. Files checked and joind together.
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//
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//
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// Revision 1.2 2001/07/03 12:55:41 mohor
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// Revision 1.2 2001/07/03 12:55:41 mohor
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// Minor changes because of the synthesys warnings.
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// Minor changes because of the synthesys warnings.
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Line 109... |
wire StartPreamble;
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wire StartPreamble;
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wire StartSFD;
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wire StartSFD;
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// Defining the next state
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// Defining the next state
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assign StartIdle = ~MRxDV & (StateDrop | StatePreamble | StateSFD | |StateData & (ByteCntEq0 | ByteCntGreat2));
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assign StartIdle = ~MRxDV & (StateDrop | StatePreamble | StateSFD | (|StateData) & (ByteCntEq0 | ByteCntGreat2));
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assign StartPreamble = MRxDV & ~MRxDEq5 & (StateIdle & ~Transmitting);
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assign StartPreamble = MRxDV & ~MRxDEq5 & (StateIdle & ~Transmitting);
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assign StartSFD = MRxDV & MRxDEq5 & (StateIdle & ~Transmitting);
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assign StartSFD = MRxDV & MRxDEq5 & (StateIdle & ~Transmitting);
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