URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_rxstatem.v] - Diff between revs 21 and 22

Rev 21	Rev 22
Line 41...	Line 41...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.3 2001/10/18 12:07:11 mohor`
	`// Status signals changed, Adress decoding changed, interrupt controller`
	`// added.`
	`//`
`// Revision 1.2 2001/09/11 14:17:00 mohor`	`// Revision 1.2 2001/09/11 14:17:00 mohor`
`// Few little NCSIM warnings fixed.`	`// Few little NCSIM warnings fixed.`
`//`	`//`
`// Revision 1.1 2001/08/06 14:44:29 mohor`	`// Revision 1.1 2001/08/06 14:44:29 mohor`
`// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).`	`// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).`
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`//`	`//`
`//`	`//`
`//`	`//`


`include "eth_timescale.v"	`include "timescale.v"


`module eth_rxstatem (MRxClk, Reset, MRxDV, ByteCntEq0, ByteCntGreat2, Transmitting, MRxDEq5, MRxDEqD,`	`module eth_rxstatem (MRxClk, Reset, MRxDV, ByteCntEq0, ByteCntGreat2, Transmitting, MRxDEq5, MRxDEqD,`
`IFGCounterEq24, ByteCntMaxFrame, StateData, StateIdle, StatePreamble, StateSFD,`	`IFGCounterEq24, ByteCntMaxFrame, StateData, StateIdle, StatePreamble, StateSFD,`
`StateDrop`	`StateDrop`