| Line 39... |
Line 39... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.5 2002/08/14 18:16:59 mohor
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// LinkFail signal was not latching appropriate bit.
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//
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// Revision 1.4 2002/03/02 21:06:01 mohor
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// Revision 1.4 2002/03/02 21:06:01 mohor
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// LinkFail signal was not latching appropriate bit.
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// LinkFail signal was not latching appropriate bit.
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//
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//
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// Revision 1.3 2002/01/23 10:28:16 mohor
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// Revision 1.3 2002/01/23 10:28:16 mohor
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// Link in the header changed.
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// Link in the header changed.
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| Line 113... |
Line 116... |
begin
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begin
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if(MdcEn_n)
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if(MdcEn_n)
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begin
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begin
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if(|ByteSelect)
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if(|ByteSelect)
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begin
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begin
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case (ByteSelect[3:0])
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case (ByteSelect[3:0]) // synopsys parallel_case full_case
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4'h1 : ShiftReg[7:0] <= #Tp {2'b01, ~WriteOp, WriteOp, Fiad[4:1]};
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4'h1 : ShiftReg[7:0] <= #Tp {2'b01, ~WriteOp, WriteOp, Fiad[4:1]};
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4'h2 : ShiftReg[7:0] <= #Tp {Fiad[0], Rgad[4:0], 2'b10};
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4'h2 : ShiftReg[7:0] <= #Tp {Fiad[0], Rgad[4:0], 2'b10};
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4'h4 : ShiftReg[7:0] <= #Tp CtrlData[15:8];
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4'h4 : ShiftReg[7:0] <= #Tp CtrlData[15:8];
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4'h8 : ShiftReg[7:0] <= #Tp CtrlData[7:0];
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4'h8 : ShiftReg[7:0] <= #Tp CtrlData[7:0];
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default : ShiftReg[7:0] <= #Tp 8'h0;
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endcase
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endcase
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end
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end
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else
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else
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begin
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begin
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ShiftReg[7:0] <= #Tp {ShiftReg[6:0], Mdi};
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ShiftReg[7:0] <= #Tp {ShiftReg[6:0], Mdi};
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