| Line 77... |
Line 77... |
|
|
module eth_shiftreg(Clk, Reset, MdcEn_n, Mdi, Fiad, Rgad, CtrlData, WriteOp, ByteSelect,
|
module eth_shiftreg(Clk, Reset, MdcEn_n, Mdi, Fiad, Rgad, CtrlData, WriteOp, ByteSelect,
|
LatchByte, ShiftedBit, Prsd, LinkFail);
|
LatchByte, ShiftedBit, Prsd, LinkFail);
|
|
|
|
|
parameter Tp=1;
|
|
|
|
input Clk; // Input clock (Host clock)
|
input Clk; // Input clock (Host clock)
|
input Reset; // Reset signal
|
input Reset; // Reset signal
|
input MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls.
|
input MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls.
|
input Mdi; // MII input data
|
input Mdi; // MII input data
|
input [4:0] Fiad; // PHY address
|
input [4:0] Fiad; // PHY address
|
| Line 106... |
Line 104... |
// ShiftReg[7:0] :: Shift Register Data
|
// ShiftReg[7:0] :: Shift Register Data
|
always @ (posedge Clk or posedge Reset)
|
always @ (posedge Clk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
begin
|
begin
|
ShiftReg[7:0] <= #Tp 8'h0;
|
ShiftReg[7:0] <= 8'h0;
|
Prsd[15:0] <= #Tp 16'h0;
|
Prsd[15:0] <= 16'h0;
|
LinkFail <= #Tp 1'b0;
|
LinkFail <= 1'b0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
if(MdcEn_n)
|
if(MdcEn_n)
|
begin
|
begin
|
if(|ByteSelect)
|
if(|ByteSelect)
|
begin
|
begin
|
case (ByteSelect[3:0]) // synopsys parallel_case full_case
|
case (ByteSelect[3:0]) // synopsys parallel_case full_case
|
4'h1 : ShiftReg[7:0] <= #Tp {2'b01, ~WriteOp, WriteOp, Fiad[4:1]};
|
4'h1 : ShiftReg[7:0] <= {2'b01, ~WriteOp, WriteOp, Fiad[4:1]};
|
4'h2 : ShiftReg[7:0] <= #Tp {Fiad[0], Rgad[4:0], 2'b10};
|
4'h2 : ShiftReg[7:0] <= {Fiad[0], Rgad[4:0], 2'b10};
|
4'h4 : ShiftReg[7:0] <= #Tp CtrlData[15:8];
|
4'h4 : ShiftReg[7:0] <= CtrlData[15:8];
|
4'h8 : ShiftReg[7:0] <= #Tp CtrlData[7:0];
|
4'h8 : ShiftReg[7:0] <= CtrlData[7:0];
|
endcase
|
endcase
|
end
|
end
|
else
|
else
|
begin
|
begin
|
ShiftReg[7:0] <= #Tp {ShiftReg[6:0], Mdi};
|
ShiftReg[7:0] <= {ShiftReg[6:0], Mdi};
|
if(LatchByte[0])
|
if(LatchByte[0])
|
begin
|
begin
|
Prsd[7:0] <= #Tp {ShiftReg[6:0], Mdi};
|
Prsd[7:0] <= {ShiftReg[6:0], Mdi};
|
if(Rgad == 5'h01)
|
if(Rgad == 5'h01)
|
LinkFail <= #Tp ~ShiftReg[1]; // this is bit [2], because it is not shifted yet
|
LinkFail <= ~ShiftReg[1]; // this is bit [2], because it is not shifted yet
|
end
|
end
|
else
|
else
|
begin
|
begin
|
if(LatchByte[1])
|
if(LatchByte[1])
|
Prsd[15:8] <= #Tp {ShiftReg[6:0], Mdi};
|
Prsd[15:8] <= {ShiftReg[6:0], Mdi};
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
