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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_shiftreg.v] - Diff between revs 352 and 355
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| Rev 352 |
Rev 355 |
| Line 114... |
Line 114... |
begin
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begin
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if(MdcEn_n)
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if(MdcEn_n)
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begin
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begin
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if(|ByteSelect)
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if(|ByteSelect)
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begin
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begin
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/* verilator lint_off CASEINCOMPLETE */
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case (ByteSelect[3:0]) // synopsys parallel_case full_case
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case (ByteSelect[3:0]) // synopsys parallel_case full_case
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4'h1 : ShiftReg[7:0] <= {2'b01, ~WriteOp, WriteOp, Fiad[4:1]};
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4'h1 : ShiftReg[7:0] <= {2'b01, ~WriteOp, WriteOp, Fiad[4:1]};
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4'h2 : ShiftReg[7:0] <= {Fiad[0], Rgad[4:0], 2'b10};
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4'h2 : ShiftReg[7:0] <= {Fiad[0], Rgad[4:0], 2'b10};
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4'h4 : ShiftReg[7:0] <= CtrlData[15:8];
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4'h4 : ShiftReg[7:0] <= CtrlData[15:8];
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4'h8 : ShiftReg[7:0] <= CtrlData[7:0];
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4'h8 : ShiftReg[7:0] <= CtrlData[7:0];
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endcase
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endcase // case (ByteSelect[3:0])
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/* verilator lint_on CASEINCOMPLETE */
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end
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end
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else
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else
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begin
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begin
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ShiftReg[7:0] <= {ShiftReg[6:0], Mdi};
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ShiftReg[7:0] <= {ShiftReg[6:0], Mdi};
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if(LatchByte[0])
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if(LatchByte[0])
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