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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_spram_256x32.v] - Diff between revs 122 and 204

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////  http://www.opencores.org/projects/ethmac/                   ////
////  http://www.opencores.org/projects/ethmac/                   ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////  Author(s):                                                  ////
////      - Igor Mohor (igorM@opencores.org)                      ////
////      - Igor Mohor (igorM@opencores.org)                      ////
////                                                              ////
////                                                              ////
////  All additional information is avaliable in the Readme.txt   ////
////  All additional information is available in the Readme.txt   ////
////  file.                                                       ////
////  file.                                                       ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
//// Copyright (C) 2001, 2002 Authors                             ////
//// Copyright (C) 2001, 2002 Authors                             ////
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//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.1  2002/07/23 16:36:09  mohor
 
// ethernet spram added. So far a generic ram and xilinx RAMB4 are used.
 
//
//
//
//
//
 
 
 
`include "eth_defines.v"
`include "timescale.v"
`include "timescale.v"
 
 
 
 
module eth_spram_256x32(
module eth_spram_256x32(
        // Generic synchronous single-port RAM interface
        // Generic synchronous single-port RAM interface
        clk, rst, ce, we, oe, addr, di, do
        clk, rst, ce, we, oe, addr, di, do
);
);
 
 
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        .CLK     (clk),
        .CLK     (clk),
        .WE      (we),
        .WE      (we),
        .RST     (rst)
        .RST     (rst)
    );
    );
 
 
`else
`else   // !ETH_XILINX_RAMB4
 
`ifdef  ETH_VIRTUAL_SILICON_RAM
 
  vs_hdsp_256x32 ram0
 
  (
 
        .CK       (clk),
 
        .CEN      (!ce),
 
        .WEN      (!we),
 
        .OEN      (!oe),
 
        .ADR      (addr),
 
        .DI       (di),
 
        .DOUT     (do)
 
  );
 
 
 
`else   // !ETH_VIRTUAL_SILICON_RAM
 
 
        //
        //
        // Generic single-port synchronous RAM model
        // Generic single-port synchronous RAM model
        //
        //
 
 
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                for (rnum=start;rnum<=finish;rnum=rnum+1)
                for (rnum=start;rnum<=finish;rnum=rnum+1)
                        $display("Addr %h = %h",rnum,mem[rnum]);
                        $display("Addr %h = %h",rnum,mem[rnum]);
        end
        end
        endtask
        endtask
 
 
`endif
`endif  // !ETH_VIRTUAL_SILICON_RAM
 
`endif  // !ETH_XILINX_RAMB4
 
 
endmodule
endmodule
 
 
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