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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_spram_256x32.v] - Diff between revs 210 and 227

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Rev 210 Rev 227
Line 39... Line 39...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.3  2002/10/10 16:29:30  mohor
 
// BIST added.
 
//
// Revision 1.2  2002/09/23 18:24:31  mohor
// Revision 1.2  2002/09/23 18:24:31  mohor
// ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation).
// ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation).
//
//
// Revision 1.1  2002/07/23 16:36:09  mohor
// Revision 1.1  2002/07/23 16:36:09  mohor
// ethernet spram added. So far a generic ram and xilinx RAMB4 are used.
// ethernet spram added. So far a generic ram and xilinx RAMB4 are used.
Line 56... Line 59...
module eth_spram_256x32(
module eth_spram_256x32(
        // Generic synchronous single-port RAM interface
        // Generic synchronous single-port RAM interface
        clk, rst, ce, we, oe, addr, di, do
        clk, rst, ce, we, oe, addr, di, do
 
 
`ifdef ETH_BIST
`ifdef ETH_BIST
  ,trst, SO, SI, shift_DR, capture_DR, extest, tck
  ,
 
  // debug chain signals
 
  scanb_rst,      // bist scan reset
 
  scanb_clk,      // bist scan clock
 
  scanb_si,       // bist scan serial in
 
  scanb_so,       // bist scan serial out
 
  scanb_en        // bist scan shift enable
`endif
`endif
 
 
 
 
 
 
);
);
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        input  [31:0]   di;   // input data bus
        input  [31:0]   di;   // input data bus
        output [31:0]   do;   // output data bus
        output [31:0]   do;   // output data bus
 
 
 
 
`ifdef ETH_BIST
`ifdef ETH_BIST
  input           trst;
  input   scanb_rst;      // bist scan reset
  input           shift_DR, capture_DR, tck, extest;
  input   scanb_clk;      // bist scan clock
  input           SI;
  input   scanb_si;       // bist scan serial in
  output          SO;
  output  scanb_so;       // bist scan serial out
 
  input   scanb_en;       // bist scan shift enable
`endif
`endif
 
 
`ifdef ETH_XILINX_RAMB4
`ifdef ETH_XILINX_RAMB4
 
 
    RAMB4_S16 ram0
    RAMB4_S16 ram0
Line 125... Line 135...
        .DI         (di),
        .DI         (di),
        .DOUT       (do)
        .DOUT       (do)
 
 
      `ifdef ETH_BIST
      `ifdef ETH_BIST
        ,
        ,
        // reset
 
        .trst      (trst),
 
 
 
        // debug chain signals
        // debug chain signals
        .SO        (SO),
        .scanb_rst      (scanb_rst),
        .SI        (SI),
        .scanb_clk      (scanb_clk),
        .shift_DR  (shift_DR),
        .scanb_si       (scanb_si),
        .capture_DR(capture_DR),
        .scanb_so       (scanb_so),
        .extest    (extest),
        .scanb_en       (scanb_en)
        .tck       (tck)
 
      `endif
      `endif
      );
      );
 
 
`else   // !ETH_VIRTUAL_SILICON_RAM
`else   // !ETH_VIRTUAL_SILICON_RAM
 
 

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