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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_spram_256x32.v] - Diff between revs 306 and 312
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| Rev 306 |
Rev 312 |
| Line 39... |
Line 39... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.8 2003/12/04 14:59:13 simons
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// Lapsus fixed (!we -> ~we).
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//
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// Revision 1.7 2003/11/12 18:24:59 tadejm
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// Revision 1.7 2003/11/12 18:24:59 tadejm
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// WISHBONE slave changed and tested from only 32-bit accesss to byte access.
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// WISHBONE slave changed and tested from only 32-bit accesss to byte access.
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//
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//
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// Revision 1.6 2003/10/17 07:46:15 markom
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// Revision 1.6 2003/10/17 07:46:15 markom
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// mbist signals updated according to newest convention
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// mbist signals updated according to newest convention
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| Line 128... |
Line 131... |
);*/
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);*/
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RAMB4_S8 ram0
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RAMB4_S8 ram0
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(
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(
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.DO (do[7:0]),
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.DO (do[7:0]),
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.ADDR (addr),
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.ADDR ({1'b0, addr}),
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.DI (di[7:0]),
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.DI (di[7:0]),
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.EN (ce),
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.EN (ce),
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.CLK (clk),
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.CLK (clk),
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.WE (we[0]),
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.WE (we[0]),
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.RST (rst)
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.RST (rst)
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);
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);
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RAMB4_S8 ram1
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RAMB4_S8 ram1
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(
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(
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.DO (do[15:8]),
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.DO (do[15:8]),
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.ADDR (addr),
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.ADDR ({1'b0, addr}),
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.DI (di[15:8]),
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.DI (di[15:8]),
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.EN (ce),
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.EN (ce),
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.CLK (clk),
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.CLK (clk),
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.WE (we[1]),
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.WE (we[1]),
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.RST (rst)
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.RST (rst)
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);
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);
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RAMB4_S8 ram2
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RAMB4_S8 ram2
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(
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(
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.DO (do[23:16]),
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.DO (do[23:16]),
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.ADDR (addr),
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.ADDR ({1'b0, addr}),
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.DI (di[23:16]),
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.DI (di[23:16]),
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.EN (ce),
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.EN (ce),
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.CLK (clk),
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.CLK (clk),
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.WE (we[2]),
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.WE (we[2]),
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.RST (rst)
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.RST (rst)
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);
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);
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RAMB4_S8 ram3
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RAMB4_S8 ram3
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(
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(
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.DO (do[31:24]),
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.DO (do[31:24]),
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.ADDR (addr),
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.ADDR ({1'b0, addr}),
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.DI (di[31:24]),
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.DI (di[31:24]),
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.EN (ce),
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.EN (ce),
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.CLK (clk),
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.CLK (clk),
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.WE (we[3]),
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.WE (we[3]),
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.RST (rst)
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.RST (rst)
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