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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_spram_256x32.v] - Diff between revs 306 and 312

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Rev 306 Rev 312
Line 39... Line 39...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.8  2003/12/04 14:59:13  simons
 
// Lapsus fixed (!we -> ~we).
 
//
// Revision 1.7  2003/11/12 18:24:59  tadejm
// Revision 1.7  2003/11/12 18:24:59  tadejm
// WISHBONE slave changed and tested from only 32-bit accesss to byte access.
// WISHBONE slave changed and tested from only 32-bit accesss to byte access.
//
//
// Revision 1.6  2003/10/17 07:46:15  markom
// Revision 1.6  2003/10/17 07:46:15  markom
// mbist signals updated according to newest convention
// mbist signals updated according to newest convention
Line 128... Line 131...
    );*/
    );*/
 
 
    RAMB4_S8 ram0
    RAMB4_S8 ram0
    (
    (
        .DO      (do[7:0]),
        .DO      (do[7:0]),
        .ADDR    (addr),
        .ADDR    ({1'b0, addr}),
        .DI      (di[7:0]),
        .DI      (di[7:0]),
        .EN      (ce),
        .EN      (ce),
        .CLK     (clk),
        .CLK     (clk),
        .WE      (we[0]),
        .WE      (we[0]),
        .RST     (rst)
        .RST     (rst)
    );
    );
 
 
    RAMB4_S8 ram1
    RAMB4_S8 ram1
    (
    (
        .DO      (do[15:8]),
        .DO      (do[15:8]),
        .ADDR    (addr),
        .ADDR    ({1'b0, addr}),
        .DI      (di[15:8]),
        .DI      (di[15:8]),
        .EN      (ce),
        .EN      (ce),
        .CLK     (clk),
        .CLK     (clk),
        .WE      (we[1]),
        .WE      (we[1]),
        .RST     (rst)
        .RST     (rst)
    );
    );
 
 
    RAMB4_S8 ram2
    RAMB4_S8 ram2
    (
    (
        .DO      (do[23:16]),
        .DO      (do[23:16]),
        .ADDR    (addr),
        .ADDR    ({1'b0, addr}),
        .DI      (di[23:16]),
        .DI      (di[23:16]),
        .EN      (ce),
        .EN      (ce),
        .CLK     (clk),
        .CLK     (clk),
        .WE      (we[2]),
        .WE      (we[2]),
        .RST     (rst)
        .RST     (rst)
    );
    );
 
 
    RAMB4_S8 ram3
    RAMB4_S8 ram3
    (
    (
        .DO      (do[31:24]),
        .DO      (do[31:24]),
        .ADDR    (addr),
        .ADDR    ({1'b0, addr}),
        .DI      (di[31:24]),
        .DI      (di[31:24]),
        .EN      (ce),
        .EN      (ce),
        .CLK     (clk),
        .CLK     (clk),
        .WE      (we[3]),
        .WE      (we[3]),
        .RST     (rst)
        .RST     (rst)

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