| Line 39... |
Line 39... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.9 2003/12/05 12:43:06 tadejm
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// Corrected address mismatch for xilinx RAMB4_S8 model which has wider address than RAMB4_S16.
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//
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// Revision 1.8 2003/12/04 14:59:13 simons
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// Revision 1.8 2003/12/04 14:59:13 simons
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// Lapsus fixed (!we -> ~we).
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// Lapsus fixed (!we -> ~we).
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//
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//
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// Revision 1.7 2003/11/12 18:24:59 tadejm
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// Revision 1.7 2003/11/12 18:24:59 tadejm
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// WISHBONE slave changed and tested from only 32-bit accesss to byte access.
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// WISHBONE slave changed and tested from only 32-bit accesss to byte access.
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| Line 228... |
Line 231... |
.mbist_ctrl_i (mbist_ctrl_i)
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.mbist_ctrl_i (mbist_ctrl_i)
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`endif
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`endif
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);
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);
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`else // !ETH_ARTISAN_RAM
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`else // !ETH_ARTISAN_RAM
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`ifdef ETH_ALTERA_ALTSYNCRAM
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|
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altera_spram_256x32 altera_spram_256x32_inst
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(
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.address (addr),
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.wren (ce & we),
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.clock (clk),
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.data (di),
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.q (do)
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); //exemplar attribute altera_spram_256x32_inst NOOPT TRUE
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`else // !ETH_ALTERA_ALTSYNCRAM
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//
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//
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// Generic single-port synchronous RAM model
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// Generic single-port synchronous RAM model
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//
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//
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|
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//
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//
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| Line 282... |
Line 299... |
for (rnum=start;rnum<=finish;rnum=rnum+1)
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for (rnum=start;rnum<=finish;rnum=rnum+1)
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$display("Addr %h = %0h %0h %0h %0h",rnum,mem3[rnum],mem2[rnum],mem1[rnum],mem0[rnum]);
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$display("Addr %h = %0h %0h %0h %0h",rnum,mem3[rnum],mem2[rnum],mem1[rnum],mem0[rnum]);
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end
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end
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endtask
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endtask
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`endif // !ETH_ALTERA_ALTSYNCRAM
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`endif // !ETH_ARTISAN_RAM
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`endif // !ETH_ARTISAN_RAM
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`endif // !ETH_VIRTUAL_SILICON_RAM
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`endif // !ETH_VIRTUAL_SILICON_RAM
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`endif // !ETH_XILINX_RAMB4
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`endif // !ETH_XILINX_RAMB4
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|
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endmodule
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endmodule
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