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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_spram_256x32.v] - Diff between revs 346 and 352

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Rev 346 Rev 352
Line 270... Line 270...
        //
        //
 
 
        // read operation
        // read operation
        always@(posedge clk)
        always@(posedge clk)
          if (ce) // && !we)
          if (ce) // && !we)
                raddr <= #1 addr;    // read address needs to be registered to read clock
                raddr <=  addr; // read address needs to be registered to read clock
 
 
        assign #1 q = rst ? {32{1'b0}} : {mem3[raddr], mem2[raddr], mem1[raddr], mem0[raddr]};
        assign #1 q = rst ? {32{1'b0}} : {mem3[raddr], mem2[raddr], mem1[raddr], mem0[raddr]};
 
 
        // write operation
        // write operation
        always@(posedge clk)
        always@(posedge clk)
        begin
        begin
                if (ce && we[3])
                if (ce && we[3])
                        mem3[addr] <= #1 di[31:24];
                  mem3[addr] <=  di[31:24];
                if (ce && we[2])
                if (ce && we[2])
                        mem2[addr] <= #1 di[23:16];
                  mem2[addr] <=  di[23:16];
                if (ce && we[1])
                if (ce && we[1])
                        mem1[addr] <= #1 di[15: 8];
                  mem1[addr] <=  di[15: 8];
                if (ce && we[0])
                if (ce && we[0])
                        mem0[addr] <= #1 di[ 7: 0];
                  mem0[addr] <=  di[ 7: 0];
        end
        end
 
 
        // Task prints range of memory
        // Task prints range of memory
        // *** Remember that tasks are non reentrant, don't call this task in parallel for multiple instantiations. 
        // *** Remember that tasks are non reentrant, don't call this task in parallel for multiple instantiations. 
        task print_ram;
        task print_ram;

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