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https://opencores.org/ocsvn/ethmac/ethmac/trunk
[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_transmitcontrol.v] - Diff between revs 352 and 353
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| Rev 352 |
Rev 353 |
| Line 248... |
Line 248... |
else
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else
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if(ResetByteCnt)
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if(ResetByteCnt)
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DlyCrcCnt <= 4'h0;
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DlyCrcCnt <= 4'h0;
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else
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else
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if(IncrementDlyCrcCnt)
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if(IncrementDlyCrcCnt)
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DlyCrcCnt <= DlyCrcCnt + 1'b1;
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DlyCrcCnt <= DlyCrcCnt + 4'd1;
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end
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end
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assign ResetByteCnt = TxReset | (~TxCtrlStartFrm & (TxDoneIn | TxAbortIn));
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assign ResetByteCnt = TxReset | (~TxCtrlStartFrm & (TxDoneIn | TxAbortIn));
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assign IncrementByteCnt = CtrlMux & (TxCtrlStartFrm & ~TxCtrlStartFrm_q & ~TxUsedDataIn | TxUsedDataIn & ~ControlEnd);
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assign IncrementByteCnt = CtrlMux & (TxCtrlStartFrm & ~TxCtrlStartFrm_q & ~TxUsedDataIn | TxUsedDataIn & ~ControlEnd);
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| Line 267... |
Line 267... |
else
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else
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if(ResetByteCnt)
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if(ResetByteCnt)
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ByteCnt <= 6'h0;
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ByteCnt <= 6'h0;
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else
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else
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if(IncrementByteCntBy2 & EnableCnt)
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if(IncrementByteCntBy2 & EnableCnt)
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ByteCnt <= (ByteCnt[5:0] ) + 2'h2;
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ByteCnt <= (ByteCnt[5:0] ) + 6'd2;
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else
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else
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if(IncrementByteCnt & EnableCnt)
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if(IncrementByteCnt & EnableCnt)
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ByteCnt <= (ByteCnt[5:0] ) + 1'b1;
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ByteCnt <= (ByteCnt[5:0] ) + 6'd1;
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end
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end
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assign ControlEnd = ByteCnt[5:0] == 6'h22;
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assign ControlEnd = ByteCnt[5:0] == 6'h22;
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