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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_txethmac.v] - Diff between revs 18 and 22

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Rev 18 Rev 22
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//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.2  2001/09/11 14:17:00  mohor
 
// Few little NCSIM warnings fixed.
 
//
// Revision 1.1  2001/08/06 14:44:29  mohor
// Revision 1.1  2001/08/06 14:44:29  mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// File eth_timescale.v is used to define timescale
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// TxEthMAC initial release.
// TxEthMAC initial release.
//
//
//
//
//
//
 
 
`include "eth_timescale.v"
`include "timescale.v"
 
 
 
 
module eth_txethmac (MTxClk, Reset, TxStartFrm, TxEndFrm, TxUnderRun, TxData, CarrierSense,
module eth_txethmac (MTxClk, Reset, TxStartFrm, TxEndFrm, TxUnderRun, TxData, CarrierSense,
                     Collision, Pad, CrcEn, FullD, HugEn, DlyCrcEn, MinFL, MaxFL, IPGT,
                     Collision, Pad, CrcEn, FullD, HugEn, DlyCrcEn, MinFL, MaxFL, IPGT,
                     IPGR1, IPGR2, CollValid, MaxRet, NoBckof, ExDfrEn,
                     IPGR1, IPGR2, CollValid, MaxRet, NoBckof, ExDfrEn,

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