//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
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//// ////
|
//// eth_txethmac.v ////
|
//// eth_txethmac.v ////
|
/// ////
|
/// ////
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//// This file is part of the Ethernet IP core project ////
|
//// This file is part of the Ethernet IP core project ////
|
//// http://www.opencores.org/project,ethmac ////
|
//// http://www.opencores.org/project,ethmac ////
|
//// ////
|
//// ////
|
//// Author(s): ////
|
//// Author(s): ////
|
//// - Igor Mohor (igorM@opencores.org) ////
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//// - Igor Mohor (igorM@opencores.org) ////
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//// - Novan Hartadi (novan@vlsi.itb.ac.id) ////
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//// - Novan Hartadi (novan@vlsi.itb.ac.id) ////
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//// - Mahmud Galela (mgalela@vlsi.itb.ac.id) ////
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//// - Mahmud Galela (mgalela@vlsi.itb.ac.id) ////
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//// ////
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//// ////
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//// All additional information is avaliable in the Readme.txt ////
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//// All additional information is avaliable in the Readme.txt ////
|
//// file. ////
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//// file. ////
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//// ////
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//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
|
//// Copyright (C) 2001 Authors ////
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//// Copyright (C) 2001 Authors ////
|
//// ////
|
//// ////
|
//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
|
//// restriction provided that this copyright statement is not ////
|
//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// ////
|
//// ////
|
//// This source file is free software; you can redistribute it ////
|
//// This source file is free software; you can redistribute it ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// later version. ////
|
//// later version. ////
|
//// ////
|
//// ////
|
//// This source is distributed in the hope that it will be ////
|
//// This source is distributed in the hope that it will be ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// details. ////
|
//// details. ////
|
//// ////
|
//// ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
|
//// Public License along with this source; if not, download it ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
// Revision 1.8 2003/01/30 13:33:24 mohor
|
// Revision 1.8 2003/01/30 13:33:24 mohor
|
// When padding was enabled and crc disabled, frame was not ended correctly.
|
// When padding was enabled and crc disabled, frame was not ended correctly.
|
//
|
//
|
// Revision 1.7 2002/02/26 16:24:01 mohor
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// Revision 1.7 2002/02/26 16:24:01 mohor
|
// RetryCntLatched was unused and removed from design
|
// RetryCntLatched was unused and removed from design
|
//
|
//
|
// Revision 1.6 2002/02/22 12:56:35 mohor
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// Revision 1.6 2002/02/22 12:56:35 mohor
|
// Retry is not activated when a Tx Underrun occured
|
// Retry is not activated when a Tx Underrun occured
|
//
|
//
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// Revision 1.5 2002/02/11 09:18:22 mohor
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// Revision 1.5 2002/02/11 09:18:22 mohor
|
// Tx status is written back to the BD.
|
// Tx status is written back to the BD.
|
//
|
//
|
// Revision 1.4 2002/01/23 10:28:16 mohor
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// Revision 1.4 2002/01/23 10:28:16 mohor
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// Link in the header changed.
|
// Link in the header changed.
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//
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//
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// Revision 1.3 2001/10/19 08:43:51 mohor
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// Revision 1.3 2001/10/19 08:43:51 mohor
|
// eth_timescale.v changed to timescale.v This is done because of the
|
// eth_timescale.v changed to timescale.v This is done because of the
|
// simulation of the few cores in a one joined project.
|
// simulation of the few cores in a one joined project.
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//
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//
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// Revision 1.2 2001/09/11 14:17:00 mohor
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// Revision 1.2 2001/09/11 14:17:00 mohor
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// Few little NCSIM warnings fixed.
|
// Few little NCSIM warnings fixed.
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//
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//
|
// Revision 1.1 2001/08/06 14:44:29 mohor
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// Revision 1.1 2001/08/06 14:44:29 mohor
|
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
|
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
|
// Include files fixed to contain no path.
|
// Include files fixed to contain no path.
|
// File names and module names changed ta have a eth_ prologue in the name.
|
// File names and module names changed ta have a eth_ prologue in the name.
|
// File eth_timescale.v is used to define timescale
|
// File eth_timescale.v is used to define timescale
|
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
|
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
|
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
|
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
|
// and Mdo_OE. The bidirectional signal must be created on the top level. This
|
// and Mdo_OE. The bidirectional signal must be created on the top level. This
|
// is done due to the ASIC tools.
|
// is done due to the ASIC tools.
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//
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//
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// Revision 1.1 2001/07/30 21:23:42 mohor
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// Revision 1.1 2001/07/30 21:23:42 mohor
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// Directory structure changed. Files checked and joind together.
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// Directory structure changed. Files checked and joind together.
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//
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//
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// Revision 1.3 2001/06/19 18:16:40 mohor
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// Revision 1.3 2001/06/19 18:16:40 mohor
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// TxClk changed to MTxClk (as discribed in the documentation).
|
// TxClk changed to MTxClk (as discribed in the documentation).
|
// Crc changed so only one file can be used instead of two.
|
// Crc changed so only one file can be used instead of two.
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//
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//
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// Revision 1.2 2001/06/19 10:38:08 mohor
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// Revision 1.2 2001/06/19 10:38:08 mohor
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// Minor changes in header.
|
// Minor changes in header.
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//
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//
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// Revision 1.1 2001/06/19 10:27:58 mohor
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// Revision 1.1 2001/06/19 10:27:58 mohor
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// TxEthMAC initial release.
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// TxEthMAC initial release.
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//
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//
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//
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//
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//
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//
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|
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`include "timescale.v"
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`include "timescale.v"
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module eth_txethmac (MTxClk, Reset, TxStartFrm, TxEndFrm, TxUnderRun, TxData, CarrierSense,
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module eth_txethmac (MTxClk, Reset, TxStartFrm, TxEndFrm, TxUnderRun, TxData, CarrierSense,
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Collision, Pad, CrcEn, FullD, HugEn, DlyCrcEn, MinFL, MaxFL, IPGT,
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Collision, Pad, CrcEn, FullD, HugEn, DlyCrcEn, MinFL, MaxFL, IPGT,
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IPGR1, IPGR2, CollValid, MaxRet, NoBckof, ExDfrEn,
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IPGR1, IPGR2, CollValid, MaxRet, NoBckof, ExDfrEn,
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MTxD, MTxEn, MTxErr, TxDone, TxRetry, TxAbort, TxUsedData, WillTransmit,
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MTxD, MTxEn, MTxErr, TxDone, TxRetry, TxAbort, TxUsedData, WillTransmit,
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ResetCollision, RetryCnt, StartTxDone, StartTxAbort, MaxCollisionOccured,
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ResetCollision, RetryCnt, StartTxDone, StartTxAbort, MaxCollisionOccured,
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LateCollision, DeferIndication, StatePreamble, StateData
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LateCollision, DeferIndication, StatePreamble, StateData
|
|
|
);
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);
|
|
|
|
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input MTxClk; // Transmit clock (from PHY)
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input MTxClk; // Transmit clock (from PHY)
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input Reset; // Reset
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input Reset; // Reset
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input TxStartFrm; // Transmit packet start frame
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input TxStartFrm; // Transmit packet start frame
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input TxEndFrm; // Transmit packet end frame
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input TxEndFrm; // Transmit packet end frame
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input TxUnderRun; // Transmit packet under-run
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input TxUnderRun; // Transmit packet under-run
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input [7:0] TxData; // Transmit packet data byte
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input [7:0] TxData; // Transmit packet data byte
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input CarrierSense; // Carrier sense (synchronized)
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input CarrierSense; // Carrier sense (synchronized)
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input Collision; // Collision (synchronized)
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input Collision; // Collision (synchronized)
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input Pad; // Pad enable (from register)
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input Pad; // Pad enable (from register)
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input CrcEn; // Crc enable (from register)
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input CrcEn; // Crc enable (from register)
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input FullD; // Full duplex (from register)
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input FullD; // Full duplex (from register)
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input HugEn; // Huge packets enable (from register)
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input HugEn; // Huge packets enable (from register)
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input DlyCrcEn; // Delayed Crc enabled (from register)
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input DlyCrcEn; // Delayed Crc enabled (from register)
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input [15:0] MinFL; // Minimum frame length (from register)
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input [15:0] MinFL; // Minimum frame length (from register)
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input [15:0] MaxFL; // Maximum frame length (from register)
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input [15:0] MaxFL; // Maximum frame length (from register)
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input [6:0] IPGT; // Back to back transmit inter packet gap parameter (from register)
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input [6:0] IPGT; // Back to back transmit inter packet gap parameter (from register)
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input [6:0] IPGR1; // Non back to back transmit inter packet gap parameter IPGR1 (from register)
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input [6:0] IPGR1; // Non back to back transmit inter packet gap parameter IPGR1 (from register)
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input [6:0] IPGR2; // Non back to back transmit inter packet gap parameter IPGR2 (from register)
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input [6:0] IPGR2; // Non back to back transmit inter packet gap parameter IPGR2 (from register)
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input [5:0] CollValid; // Valid collision window (from register)
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input [5:0] CollValid; // Valid collision window (from register)
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input [3:0] MaxRet; // Maximum retry number (from register)
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input [3:0] MaxRet; // Maximum retry number (from register)
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input NoBckof; // No backoff (from register)
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input NoBckof; // No backoff (from register)
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input ExDfrEn; // Excessive defferal enable (from register)
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input ExDfrEn; // Excessive defferal enable (from register)
|
|
|
output [3:0] MTxD; // Transmit nibble (to PHY)
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output [3:0] MTxD; // Transmit nibble (to PHY)
|
output MTxEn; // Transmit enable (to PHY)
|
output MTxEn; // Transmit enable (to PHY)
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output MTxErr; // Transmit error (to PHY)
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output MTxErr; // Transmit error (to PHY)
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output TxDone; // Transmit packet done (to RISC)
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output TxDone; // Transmit packet done (to RISC)
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output TxRetry; // Transmit packet retry (to RISC)
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output TxRetry; // Transmit packet retry (to RISC)
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output TxAbort; // Transmit packet abort (to RISC)
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output TxAbort; // Transmit packet abort (to RISC)
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output TxUsedData; // Transmit packet used data (to RISC)
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output TxUsedData; // Transmit packet used data (to RISC)
|
output WillTransmit; // Will transmit (to RxEthMAC)
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output WillTransmit; // Will transmit (to RxEthMAC)
|
output ResetCollision; // Reset Collision (for synchronizing collision)
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output ResetCollision; // Reset Collision (for synchronizing collision)
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output [3:0] RetryCnt; // Latched Retry Counter for tx status purposes
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output [3:0] RetryCnt; // Latched Retry Counter for tx status purposes
|
output StartTxDone;
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output StartTxDone;
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output StartTxAbort;
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output StartTxAbort;
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output MaxCollisionOccured;
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output MaxCollisionOccured;
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output LateCollision;
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output LateCollision;
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output DeferIndication;
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output DeferIndication;
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output StatePreamble;
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output StatePreamble;
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output [1:0] StateData;
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output [1:0] StateData;
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|
|
reg [3:0] MTxD;
|
reg [3:0] MTxD;
|
reg MTxEn;
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reg MTxEn;
|
reg MTxErr;
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reg MTxErr;
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reg TxDone;
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reg TxDone;
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reg TxRetry;
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reg TxRetry;
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reg TxAbort;
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reg TxAbort;
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reg TxUsedData;
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reg TxUsedData;
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reg WillTransmit;
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reg WillTransmit;
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reg ColWindow;
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reg ColWindow;
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reg StopExcessiveDeferOccured;
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reg StopExcessiveDeferOccured;
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reg [3:0] RetryCnt;
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reg [3:0] RetryCnt;
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reg [3:0] MTxD_d;
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reg [3:0] MTxD_d;
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reg StatusLatch;
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reg StatusLatch;
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reg PacketFinished_q;
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reg PacketFinished_q;
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reg PacketFinished;
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reg PacketFinished;
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|
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|
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wire ExcessiveDeferOccured;
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wire ExcessiveDeferOccured;
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wire StartIPG;
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wire StartIPG;
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wire StartPreamble;
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wire StartPreamble;
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wire [1:0] StartData;
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wire [1:0] StartData;
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wire StartFCS;
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wire StartFCS;
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wire StartJam;
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wire StartJam;
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wire StartDefer;
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wire StartDefer;
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wire StartBackoff;
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wire StartBackoff;
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wire StateDefer;
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wire StateDefer;
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wire StateIPG;
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wire StateIPG;
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wire StateIdle;
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wire StateIdle;
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wire StatePAD;
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wire StatePAD;
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wire StateFCS;
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wire StateFCS;
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wire StateJam;
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wire StateJam;
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wire StateJam_q;
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wire StateJam_q;
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wire StateBackOff;
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wire StateBackOff;
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wire StateSFD;
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wire StateSFD;
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wire StartTxRetry;
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wire StartTxRetry;
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wire UnderRun;
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wire UnderRun;
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wire TooBig;
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wire TooBig;
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wire [31:0] Crc;
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wire [31:0] Crc;
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wire CrcError;
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wire CrcError;
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wire [2:0] DlyCrcCnt;
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wire [2:0] DlyCrcCnt;
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wire [15:0] NibCnt;
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wire [15:0] NibCnt;
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wire NibCntEq7;
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wire NibCntEq7;
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wire NibCntEq15;
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wire NibCntEq15;
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wire NibbleMinFl;
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wire NibbleMinFl;
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wire ExcessiveDefer;
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wire ExcessiveDefer;
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wire [15:0] ByteCnt;
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wire [15:0] ByteCnt;
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wire MaxFrame;
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wire MaxFrame;
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wire RetryMax;
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wire RetryMax;
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wire RandomEq0;
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wire RandomEq0;
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wire RandomEqByteCnt;
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wire RandomEqByteCnt;
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wire PacketFinished_d;
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wire PacketFinished_d;
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assign ResetCollision = ~(StatePreamble | (|StateData) | StatePAD | StateFCS);
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assign ResetCollision = ~(StatePreamble | (|StateData) | StatePAD | StateFCS);
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|
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assign ExcessiveDeferOccured = TxStartFrm & StateDefer & ExcessiveDefer & ~StopExcessiveDeferOccured;
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assign ExcessiveDeferOccured = TxStartFrm & StateDefer & ExcessiveDefer & ~StopExcessiveDeferOccured;
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|
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assign StartTxDone = ~Collision & (StateFCS & NibCntEq7 | StateData[1] & TxEndFrm & (~Pad | Pad & NibbleMinFl) & ~CrcEn);
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assign StartTxDone = ~Collision & (StateFCS & NibCntEq7 | StateData[1] & TxEndFrm & (~Pad | Pad & NibbleMinFl) & ~CrcEn);
|
|
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assign UnderRun = StateData[0] & TxUnderRun & ~Collision;
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assign UnderRun = StateData[0] & TxUnderRun & ~Collision;
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|
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assign TooBig = ~Collision & MaxFrame & (StateData[0] & ~TxUnderRun | StateFCS);
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assign TooBig = ~Collision & MaxFrame & (StateData[0] & ~TxUnderRun | StateFCS);
|
|
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// assign StartTxRetry = StartJam & (ColWindow & ~RetryMax);
|
// assign StartTxRetry = StartJam & (ColWindow & ~RetryMax);
|
assign StartTxRetry = StartJam & (ColWindow & ~RetryMax) & ~UnderRun;
|
assign StartTxRetry = StartJam & (ColWindow & ~RetryMax) & ~UnderRun;
|
|
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assign LateCollision = StartJam & ~ColWindow & ~UnderRun;
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assign LateCollision = StartJam & ~ColWindow & ~UnderRun;
|
|
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assign MaxCollisionOccured = StartJam & ColWindow & RetryMax;
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assign MaxCollisionOccured = StartJam & ColWindow & RetryMax;
|
|
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assign StateSFD = StatePreamble & NibCntEq15;
|
assign StateSFD = StatePreamble & NibCntEq15;
|
|
|
assign StartTxAbort = TooBig | UnderRun | ExcessiveDeferOccured | LateCollision | MaxCollisionOccured;
|
assign StartTxAbort = TooBig | UnderRun | ExcessiveDeferOccured | LateCollision | MaxCollisionOccured;
|
|
|
|
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// StopExcessiveDeferOccured
|
// StopExcessiveDeferOccured
|
always @ (posedge MTxClk or posedge Reset)
|
always @ (posedge MTxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
StopExcessiveDeferOccured <= 1'b0;
|
StopExcessiveDeferOccured <= 1'b0;
|
else
|
else
|
begin
|
begin
|
if(~TxStartFrm)
|
if(~TxStartFrm)
|
StopExcessiveDeferOccured <= 1'b0;
|
StopExcessiveDeferOccured <= 1'b0;
|
else
|
else
|
if(ExcessiveDeferOccured)
|
if(ExcessiveDeferOccured)
|
StopExcessiveDeferOccured <= 1'b1;
|
StopExcessiveDeferOccured <= 1'b1;
|
end
|
end
|
end
|
end
|
|
|
|
|
// Collision Window
|
// Collision Window
|
always @ (posedge MTxClk or posedge Reset)
|
always @ (posedge MTxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
ColWindow <= 1'b1;
|
ColWindow <= 1'b1;
|
else
|
else
|
begin
|
begin
|
if(~Collision & ByteCnt[5:0] == CollValid[5:0] & (StateData[1] | StatePAD & NibCnt[0] | StateFCS & NibCnt[0]))
|
if(~Collision & ByteCnt[5:0] == CollValid[5:0] & (StateData[1] | StatePAD & NibCnt[0] | StateFCS & NibCnt[0]))
|
ColWindow <= 1'b0;
|
ColWindow <= 1'b0;
|
else
|
else
|
if(StateIdle | StateIPG)
|
if(StateIdle | StateIPG)
|
ColWindow <= 1'b1;
|
ColWindow <= 1'b1;
|
end
|
end
|
end
|
end
|
|
|
|
|
// Start Window
|
// Start Window
|
always @ (posedge MTxClk or posedge Reset)
|
always @ (posedge MTxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
StatusLatch <= 1'b0;
|
StatusLatch <= 1'b0;
|
else
|
else
|
begin
|
begin
|
if(~TxStartFrm)
|
if(~TxStartFrm)
|
StatusLatch <= 1'b0;
|
StatusLatch <= 1'b0;
|
else
|
else
|
if(ExcessiveDeferOccured | StateIdle)
|
if(ExcessiveDeferOccured | StateIdle)
|
StatusLatch <= 1'b1;
|
StatusLatch <= 1'b1;
|
end
|
end
|
end
|
end
|
|
|
|
|
// Transmit packet used data
|
// Transmit packet used data
|
always @ (posedge MTxClk or posedge Reset)
|
always @ (posedge MTxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
TxUsedData <= 1'b0;
|
TxUsedData <= 1'b0;
|
else
|
else
|
TxUsedData <= |StartData;
|
TxUsedData <= |StartData;
|
end
|
end
|
|
|
|
|
// Transmit packet done
|
// Transmit packet done
|
always @ (posedge MTxClk or posedge Reset)
|
always @ (posedge MTxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
TxDone <= 1'b0;
|
TxDone <= 1'b0;
|
else
|
else
|
begin
|
begin
|
if(TxStartFrm & ~StatusLatch)
|
if(TxStartFrm & ~StatusLatch)
|
TxDone <= 1'b0;
|
TxDone <= 1'b0;
|
else
|
else
|
if(StartTxDone)
|
if(StartTxDone)
|
TxDone <= 1'b1;
|
TxDone <= 1'b1;
|
end
|
end
|
end
|
end
|
|
|
|
|
// Transmit packet retry
|
// Transmit packet retry
|
always @ (posedge MTxClk or posedge Reset)
|
always @ (posedge MTxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
TxRetry <= 1'b0;
|
TxRetry <= 1'b0;
|
else
|
else
|
begin
|
begin
|
if(TxStartFrm & ~StatusLatch)
|
if(TxStartFrm & ~StatusLatch)
|
TxRetry <= 1'b0;
|
TxRetry <= 1'b0;
|
else
|
else
|
if(StartTxRetry)
|
if(StartTxRetry)
|
TxRetry <= 1'b1;
|
TxRetry <= 1'b1;
|
end
|
end
|
end
|
end
|
|
|
|
|
// Transmit packet abort
|
// Transmit packet abort
|
always @ (posedge MTxClk or posedge Reset)
|
always @ (posedge MTxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
TxAbort <= 1'b0;
|
TxAbort <= 1'b0;
|
else
|
else
|
begin
|
begin
|
if(TxStartFrm & ~StatusLatch & ~ExcessiveDeferOccured)
|
if(TxStartFrm & ~StatusLatch & ~ExcessiveDeferOccured)
|
TxAbort <= 1'b0;
|
TxAbort <= 1'b0;
|
else
|
else
|
if(StartTxAbort)
|
if(StartTxAbort)
|
TxAbort <= 1'b1;
|
TxAbort <= 1'b1;
|
end
|
end
|
end
|
end
|
|
|
|
|
// Retry counter
|
// Retry counter
|
always @ (posedge MTxClk or posedge Reset)
|
always @ (posedge MTxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
RetryCnt[3:0] <= 4'h0;
|
RetryCnt[3:0] <= 4'h0;
|
else
|
else
|
begin
|
begin
|
if(ExcessiveDeferOccured | UnderRun | TooBig | StartTxDone | TxUnderRun
|
if(ExcessiveDeferOccured | UnderRun | TooBig | StartTxDone | TxUnderRun
|
| StateJam & NibCntEq7 & (~ColWindow | RetryMax))
|
| StateJam & NibCntEq7 & (~ColWindow | RetryMax))
|
RetryCnt[3:0] <= 4'h0;
|
RetryCnt[3:0] <= 4'h0;
|
else
|
else
|
if(StateJam & NibCntEq7 & ColWindow & (RandomEq0 | NoBckof) | StateBackOff & RandomEqByteCnt)
|
if(StateJam & NibCntEq7 & ColWindow & (RandomEq0 | NoBckof) | StateBackOff & RandomEqByteCnt)
|
RetryCnt[3:0] <= RetryCnt[3:0] + 1'b1;
|
RetryCnt[3:0] <= RetryCnt[3:0] + 1;
|
end
|
end
|
end
|
end
|
|
|
|
|
assign RetryMax = RetryCnt[3:0] == MaxRet[3:0];
|
assign RetryMax = RetryCnt[3:0] == MaxRet[3:0];
|
|
|
|
|
// Transmit nibble
|
// Transmit nibble
|
always @ (StatePreamble or StateData or StateData or StateFCS or StateJam or StateSFD or TxData or
|
always @ (StatePreamble or StateData or StateData or StateFCS or StateJam or StateSFD or TxData or
|
Crc or NibCntEq15)
|
Crc or NibCntEq15)
|
begin
|
begin
|
if(StateData[0])
|
if(StateData[0])
|
MTxD_d[3:0] = TxData[3:0]; // Lower nibble
|
MTxD_d[3:0] = TxData[3:0]; // Lower nibble
|
else
|
else
|
if(StateData[1])
|
if(StateData[1])
|
MTxD_d[3:0] = TxData[7:4]; // Higher nibble
|
MTxD_d[3:0] = TxData[7:4]; // Higher nibble
|
else
|
else
|
if(StateFCS)
|
if(StateFCS)
|
MTxD_d[3:0] = {~Crc[28], ~Crc[29], ~Crc[30], ~Crc[31]}; // Crc
|
MTxD_d[3:0] = {~Crc[28], ~Crc[29], ~Crc[30], ~Crc[31]}; // Crc
|
else
|
else
|
if(StateJam)
|
if(StateJam)
|
MTxD_d[3:0] = 4'h9; // Jam pattern
|
MTxD_d[3:0] = 4'h9; // Jam pattern
|
else
|
else
|
if(StatePreamble)
|
if(StatePreamble)
|
if(NibCntEq15)
|
if(NibCntEq15)
|
MTxD_d[3:0] = 4'hd; // SFD
|
MTxD_d[3:0] = 4'hd; // SFD
|
else
|
else
|
MTxD_d[3:0] = 4'h5; // Preamble
|
MTxD_d[3:0] = 4'h5; // Preamble
|
else
|
else
|
MTxD_d[3:0] = 4'h0;
|
MTxD_d[3:0] = 4'h0;
|
end
|
end
|
|
|
|
|
// Transmit Enable
|
// Transmit Enable
|
always @ (posedge MTxClk or posedge Reset)
|
always @ (posedge MTxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
MTxEn <= 1'b0;
|
MTxEn <= 1'b0;
|
else
|
else
|
MTxEn <= StatePreamble | (|StateData) | StatePAD | StateFCS | StateJam;
|
MTxEn <= StatePreamble | (|StateData) | StatePAD | StateFCS | StateJam;
|
end
|
end
|
|
|
|
|
// Transmit nibble
|
// Transmit nibble
|
always @ (posedge MTxClk or posedge Reset)
|
always @ (posedge MTxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
MTxD[3:0] <= 4'h0;
|
MTxD[3:0] <= 4'h0;
|
else
|
else
|
MTxD[3:0] <= MTxD_d[3:0];
|
MTxD[3:0] <= MTxD_d[3:0];
|
end
|
end
|
|
|
|
|
// Transmit error
|
// Transmit error
|
always @ (posedge MTxClk or posedge Reset)
|
always @ (posedge MTxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
MTxErr <= 1'b0;
|
MTxErr <= 1'b0;
|
else
|
else
|
MTxErr <= TooBig | UnderRun;
|
MTxErr <= TooBig | UnderRun;
|
end
|
end
|
|
|
|
|
// WillTransmit
|
// WillTransmit
|
always @ (posedge MTxClk or posedge Reset)
|
always @ (posedge MTxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
WillTransmit <= 1'b0;
|
WillTransmit <= 1'b0;
|
else
|
else
|
WillTransmit <= StartPreamble | StatePreamble | (|StateData) | StatePAD | StateFCS | StateJam;
|
WillTransmit <= StartPreamble | StatePreamble | (|StateData) | StatePAD | StateFCS | StateJam;
|
end
|
end
|
|
|
|
|
assign PacketFinished_d = StartTxDone | TooBig | UnderRun | LateCollision | MaxCollisionOccured | ExcessiveDeferOccured;
|
assign PacketFinished_d = StartTxDone | TooBig | UnderRun | LateCollision | MaxCollisionOccured | ExcessiveDeferOccured;
|
|
|
|
|
// Packet finished
|
// Packet finished
|
always @ (posedge MTxClk or posedge Reset)
|
always @ (posedge MTxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
begin
|
begin
|
PacketFinished <= 1'b0;
|
PacketFinished <= 1'b0;
|
PacketFinished_q <= 1'b0;
|
PacketFinished_q <= 1'b0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
PacketFinished <= PacketFinished_d;
|
PacketFinished <= PacketFinished_d;
|
PacketFinished_q <= PacketFinished;
|
PacketFinished_q <= PacketFinished;
|
end
|
end
|
end
|
end
|
|
|
|
|
// Connecting module Counters
|
// Connecting module Counters
|
eth_txcounters txcounters1 (.StatePreamble(StatePreamble), .StateIPG(StateIPG), .StateData(StateData),
|
eth_txcounters txcounters1 (.StatePreamble(StatePreamble), .StateIPG(StateIPG), .StateData(StateData),
|
.StatePAD(StatePAD), .StateFCS(StateFCS), .StateJam(StateJam), .StateBackOff(StateBackOff),
|
.StatePAD(StatePAD), .StateFCS(StateFCS), .StateJam(StateJam), .StateBackOff(StateBackOff),
|
.StateDefer(StateDefer), .StateIdle(StateIdle), .StartDefer(StartDefer), .StartIPG(StartIPG),
|
.StateDefer(StateDefer), .StateIdle(StateIdle), .StartDefer(StartDefer), .StartIPG(StartIPG),
|
.StartFCS(StartFCS), .StartJam(StartJam), .TxStartFrm(TxStartFrm), .MTxClk(MTxClk),
|
.StartFCS(StartFCS), .StartJam(StartJam), .TxStartFrm(TxStartFrm), .MTxClk(MTxClk),
|
.Reset(Reset), .MinFL(MinFL), .MaxFL(MaxFL), .HugEn(HugEn), .ExDfrEn(ExDfrEn),
|
.Reset(Reset), .MinFL(MinFL), .MaxFL(MaxFL), .HugEn(HugEn), .ExDfrEn(ExDfrEn),
|
.PacketFinished_q(PacketFinished_q), .DlyCrcEn(DlyCrcEn), .StartBackoff(StartBackoff),
|
.PacketFinished_q(PacketFinished_q), .DlyCrcEn(DlyCrcEn), .StartBackoff(StartBackoff),
|
.StateSFD(StateSFD), .ByteCnt(ByteCnt), .NibCnt(NibCnt), .ExcessiveDefer(ExcessiveDefer),
|
.StateSFD(StateSFD), .ByteCnt(ByteCnt), .NibCnt(NibCnt), .ExcessiveDefer(ExcessiveDefer),
|
.NibCntEq7(NibCntEq7), .NibCntEq15(NibCntEq15), .MaxFrame(MaxFrame), .NibbleMinFl(NibbleMinFl),
|
.NibCntEq7(NibCntEq7), .NibCntEq15(NibCntEq15), .MaxFrame(MaxFrame), .NibbleMinFl(NibbleMinFl),
|
.DlyCrcCnt(DlyCrcCnt)
|
.DlyCrcCnt(DlyCrcCnt)
|
);
|
);
|
|
|
|
|
// Connecting module StateM
|
// Connecting module StateM
|
eth_txstatem txstatem1 (.MTxClk(MTxClk), .Reset(Reset), .ExcessiveDefer(ExcessiveDefer), .CarrierSense(CarrierSense),
|
eth_txstatem txstatem1 (.MTxClk(MTxClk), .Reset(Reset), .ExcessiveDefer(ExcessiveDefer), .CarrierSense(CarrierSense),
|
.NibCnt(NibCnt[6:0]), .IPGT(IPGT), .IPGR1(IPGR1), .IPGR2(IPGR2), .FullD(FullD),
|
.NibCnt(NibCnt[6:0]), .IPGT(IPGT), .IPGR1(IPGR1), .IPGR2(IPGR2), .FullD(FullD),
|
.TxStartFrm(TxStartFrm), .TxEndFrm(TxEndFrm), .TxUnderRun(TxUnderRun), .Collision(Collision),
|
.TxStartFrm(TxStartFrm), .TxEndFrm(TxEndFrm), .TxUnderRun(TxUnderRun), .Collision(Collision),
|
.UnderRun(UnderRun), .StartTxDone(StartTxDone), .TooBig(TooBig), .NibCntEq7(NibCntEq7),
|
.UnderRun(UnderRun), .StartTxDone(StartTxDone), .TooBig(TooBig), .NibCntEq7(NibCntEq7),
|
.NibCntEq15(NibCntEq15), .MaxFrame(MaxFrame), .Pad(Pad), .CrcEn(CrcEn),
|
.NibCntEq15(NibCntEq15), .MaxFrame(MaxFrame), .Pad(Pad), .CrcEn(CrcEn),
|
.NibbleMinFl(NibbleMinFl), .RandomEq0(RandomEq0), .ColWindow(ColWindow), .RetryMax(RetryMax),
|
.NibbleMinFl(NibbleMinFl), .RandomEq0(RandomEq0), .ColWindow(ColWindow), .RetryMax(RetryMax),
|
.NoBckof(NoBckof), .RandomEqByteCnt(RandomEqByteCnt), .StateIdle(StateIdle),
|
.NoBckof(NoBckof), .RandomEqByteCnt(RandomEqByteCnt), .StateIdle(StateIdle),
|
.StateIPG(StateIPG), .StatePreamble(StatePreamble), .StateData(StateData), .StatePAD(StatePAD),
|
.StateIPG(StateIPG), .StatePreamble(StatePreamble), .StateData(StateData), .StatePAD(StatePAD),
|
.StateFCS(StateFCS), .StateJam(StateJam), .StateJam_q(StateJam_q), .StateBackOff(StateBackOff),
|
.StateFCS(StateFCS), .StateJam(StateJam), .StateJam_q(StateJam_q), .StateBackOff(StateBackOff),
|
.StateDefer(StateDefer), .StartFCS(StartFCS), .StartJam(StartJam), .StartBackoff(StartBackoff),
|
.StateDefer(StateDefer), .StartFCS(StartFCS), .StartJam(StartJam), .StartBackoff(StartBackoff),
|
.StartDefer(StartDefer), .DeferIndication(DeferIndication), .StartPreamble(StartPreamble), .StartData(StartData), .StartIPG(StartIPG)
|
.StartDefer(StartDefer), .DeferIndication(DeferIndication), .StartPreamble(StartPreamble), .StartData(StartData), .StartIPG(StartIPG)
|
);
|
);
|
|
|
|
|
wire Enable_Crc;
|
wire Enable_Crc;
|
wire [3:0] Data_Crc;
|
wire [3:0] Data_Crc;
|
wire Initialize_Crc;
|
wire Initialize_Crc;
|
|
|
assign Enable_Crc = ~StateFCS;
|
assign Enable_Crc = ~StateFCS;
|
|
|
assign Data_Crc[0] = StateData[0]? TxData[3] : StateData[1]? TxData[7] : 1'b0;
|
assign Data_Crc[0] = StateData[0]? TxData[3] : StateData[1]? TxData[7] : 1'b0;
|
assign Data_Crc[1] = StateData[0]? TxData[2] : StateData[1]? TxData[6] : 1'b0;
|
assign Data_Crc[1] = StateData[0]? TxData[2] : StateData[1]? TxData[6] : 1'b0;
|
assign Data_Crc[2] = StateData[0]? TxData[1] : StateData[1]? TxData[5] : 1'b0;
|
assign Data_Crc[2] = StateData[0]? TxData[1] : StateData[1]? TxData[5] : 1'b0;
|
assign Data_Crc[3] = StateData[0]? TxData[0] : StateData[1]? TxData[4] : 1'b0;
|
assign Data_Crc[3] = StateData[0]? TxData[0] : StateData[1]? TxData[4] : 1'b0;
|
|
|
assign Initialize_Crc = StateIdle | StatePreamble | (|DlyCrcCnt);
|
assign Initialize_Crc = StateIdle | StatePreamble | (|DlyCrcCnt);
|
|
|
|
|
// Connecting module Crc
|
// Connecting module Crc
|
eth_crc txcrc (.Clk(MTxClk), .Reset(Reset), .Data(Data_Crc), .Enable(Enable_Crc), .Initialize(Initialize_Crc),
|
eth_crc txcrc (.Clk(MTxClk), .Reset(Reset), .Data(Data_Crc), .Enable(Enable_Crc), .Initialize(Initialize_Crc),
|
.Crc(Crc), .CrcError(CrcError)
|
.Crc(Crc), .CrcError(CrcError)
|
);
|
);
|
|
|
|
|
// Connecting module Random
|
// Connecting module Random
|
eth_random random1 (.MTxClk(MTxClk), .Reset(Reset), .StateJam(StateJam), .StateJam_q(StateJam_q), .RetryCnt(RetryCnt),
|
eth_random random1 (.MTxClk(MTxClk), .Reset(Reset), .StateJam(StateJam), .StateJam_q(StateJam_q), .RetryCnt(RetryCnt),
|
.NibCnt(NibCnt), .ByteCnt(ByteCnt[9:0]), .RandomEq0(RandomEq0), .RandomEqByteCnt(RandomEqByteCnt));
|
.NibCnt(NibCnt), .ByteCnt(ByteCnt[9:0]), .RandomEq0(RandomEq0), .RandomEqByteCnt(RandomEqByteCnt));
|
|
|
|
|
|
|
|
|
endmodule
|
endmodule
|
|
|
