URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_wishbone.v] - Diff between revs 164 and 166

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 164	Rev 166
Line 6...	Line 6...
`//// http://www.opencores.org/projects/ethmac/ ////`	`//// http://www.opencores.org/projects/ethmac/ ////`
`//// ////`	`//// ////`
`//// Author(s): ////`	`//// Author(s): ////`
`//// - Igor Mohor (igorM@opencores.org) ////`	`//// - Igor Mohor (igorM@opencores.org) ////`
`//// ////`	`//// ////`
`//// All additional information is avaliable in the Readme.txt ////`	`//// All additional information is available in the Readme.txt ////`
`//// file. ////`	`//// file. ////`
`//// ////`	`//// ////`
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//// ////`	`//// ////`
`//// Copyright (C) 2001, 2002 Authors ////`	`//// Copyright (C) 2001, 2002 Authors ////`
Line 39...	Line 39...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.35 2002/09/10 10:35:23 mohor`
	`// Ethernet debug registers removed.`
	`//`
`// Revision 1.34 2002/09/08 16:31:49 mohor`	`// Revision 1.34 2002/09/08 16:31:49 mohor`
`// Async reset for WB_ACK_O removed (when core was in reset, it was`	`// Async reset for WB_ACK_O removed (when core was in reset, it was`
`// impossible to access BDs).`	`// impossible to access BDs).`
`// RxPointers and TxPointers names changed to be more descriptive.`	`// RxPointers and TxPointers names changed to be more descriptive.`
`// TxUnderRun synchronized.`	`// TxUnderRun synchronized.`
Line 289...	Line 292...
`reg TxB_IRQ;`	`reg TxB_IRQ;`
`reg TxE_IRQ;`	`reg TxE_IRQ;`
`reg RxB_IRQ;`	`reg RxB_IRQ;`
`reg RxE_IRQ;`	`reg RxE_IRQ;`


`reg TxStartFrm;`	`reg TxStartFrm;`
`reg TxEndFrm;`	`reg TxEndFrm;`
`reg [7:0] TxData;`	`reg [7:0] TxData;`

`reg TxUnderRun;`	`reg TxUnderRun;`
Line 320...	Line 322...
`reg TxRetry_wb_q;`	`reg TxRetry_wb_q;`
`reg TxDone_wb_q2;`	`reg TxDone_wb_q2;`
`reg TxAbort_wb_q2;`	`reg TxAbort_wb_q2;`
`reg TxRetry_wb_q2;`	`reg TxRetry_wb_q2;`
`reg RxBDReady;`	`reg RxBDReady;`
	`reg RxReady;`
`reg TxBDReady;`	`reg TxBDReady;`

`reg RxBDRead;`	`reg RxBDRead;`
`wire RxStatusWrite;`	`wire RxStatusWrite;`

Line 1521...	Line 1524...
`always @ (posedge WB_CLK_I or posedge Reset)`	`always @ (posedge WB_CLK_I or posedge Reset)`
`begin`	`begin`
`if(Reset)`	`if(Reset)`
`RxBDRead <=#Tp 1'b1;`	`RxBDRead <=#Tp 1'b1;`
`else`	`else`
`if(StartRxBDRead & ~RxBDReady)`	`if(StartRxBDRead & ~RxReady)`
`RxBDRead <=#Tp 1'b1;`	`RxBDRead <=#Tp 1'b1;`
`else`	`else`
`if(RxBDReady)`	`if(RxBDReady)`
`RxBDRead <=#Tp 1'b0;`	`RxBDRead <=#Tp 1'b0;`
`end`	`end`
Line 1538...	Line 1541...
`always @ (posedge WB_CLK_I or posedge Reset)`	`always @ (posedge WB_CLK_I or posedge Reset)`
`begin`	`begin`
`if(Reset)`	`if(Reset)`
`RxBDReady <=#Tp 1'b0;`	`RxBDReady <=#Tp 1'b0;`
`else`	`else`
`if(ShiftEnded \| RxAbortSync2 & ~RxAbortSync3)`	`if(RxPointerRead)`
`RxBDReady <=#Tp 1'b0;`	`RxBDReady <=#Tp 1'b0;`
`else`	`else`
`if(RxEn & RxEn_q & RxBDRead)`	`if(RxEn & RxEn_q & RxBDRead)`
`RxBDReady <=#Tp ram_do[15]; // RxBDReady is sampled only once at the beginning`	`RxBDReady <=#Tp ram_do[15]; // RxBDReady is sampled only once at the beginning`
`end`	`end`
Line 1557...	Line 1560...
`if(RxEn & RxEn_q & RxBDRead)`	`if(RxEn & RxEn_q & RxBDRead)`
`RxStatus <=#Tp ram_do[14:13];`	`RxStatus <=#Tp ram_do[14:13];`
`end`	`end`


	`// RxReady generation`
	`always @ (posedge WB_CLK_I or posedge Reset)`
	`begin`
	`if(Reset)`
	`RxReady <=#Tp 1'b0;`
	`else`
	`if(ShiftEnded \| RxAbortSync2 & ~RxAbortSync3)`
	`RxReady <=#Tp 1'b0;`
	`else`
	`if(RxEn & RxEn_q & RxPointerRead)`
	`RxReady <=#Tp 1'b1;`
	`end`


`// Reading Rx BD pointer`	`// Reading Rx BD pointer`


Line 1573...	Line 1588...
`RxPointerRead <=#Tp 1'b0;`	`RxPointerRead <=#Tp 1'b0;`
`else`	`else`
`if(StartRxPointerRead)`	`if(StartRxPointerRead)`
`RxPointerRead <=#Tp 1'b1;`	`RxPointerRead <=#Tp 1'b1;`
`else`	`else`
`if(RxEn_q)`	`if(RxEn & RxEn_q)`
`RxPointerRead <=#Tp 1'b0;`	`RxPointerRead <=#Tp 1'b0;`
`end`	`end`


`//Latching Rx buffer pointer from buffer descriptor;`	`//Latching Rx buffer pointer from buffer descriptor;`
Line 1622...	Line 1637...
`always @ (posedge WB_CLK_I or posedge Reset)`	`always @ (posedge WB_CLK_I or posedge Reset)`
`begin`	`begin`
`if(Reset)`	`if(Reset)`
`RxEn_needed <=#Tp 1'b0;`	`RxEn_needed <=#Tp 1'b0;`
`else`	`else`
`if(~RxBDReady & r_RxEn & WbEn & ~WbEn_q)`	`if(~RxReady & r_RxEn & WbEn & ~WbEn_q)`
`RxEn_needed <=#Tp 1'b1;`	`RxEn_needed <=#Tp 1'b1;`
`else`	`else`
`if(RxPointerRead & RxEn & RxEn_q)`	`if(RxPointerRead & RxEn & RxEn_q)`
`RxEn_needed <=#Tp 1'b0;`	`RxEn_needed <=#Tp 1'b0;`
`end`	`end`
Line 1672...	Line 1687...
`LastByteIn <=#Tp 1'b0;`	`LastByteIn <=#Tp 1'b0;`
`else`	`else`
`if(ShiftWillEnd & (&RxByteCnt) \| RxAbort)`	`if(ShiftWillEnd & (&RxByteCnt) \| RxAbort)`
`LastByteIn <=#Tp 1'b0;`	`LastByteIn <=#Tp 1'b0;`
`else`	`else`
`if(RxValid & RxBDReady & RxEndFrm & ~(&RxByteCnt) & RxEnableWindow)`	`if(RxValid & RxReady & RxEndFrm & ~(&RxByteCnt) & RxEnableWindow)`
`LastByteIn <=#Tp 1'b1;`	`LastByteIn <=#Tp 1'b1;`
`end`	`end`

`reg ShiftEnded_rck;`	`reg ShiftEnded_rck;`
`reg ShiftEndedSync1;`	`reg ShiftEndedSync1;`
Line 1710...	Line 1725...
`RxByteCnt <=#Tp 2'h0;`	`RxByteCnt <=#Tp 2'h0;`
`else`	`else`
`if(ShiftEnded_rck \| RxAbort)`	`if(ShiftEnded_rck \| RxAbort)`
`RxByteCnt <=#Tp 2'h0;`	`RxByteCnt <=#Tp 2'h0;`
`else`	`else`
`if(RxValid & RxStartFrm & RxBDReady)`	`if(RxValid & RxStartFrm & RxReady)`
`case(RxPointerLSB_rst) // synopsys parallel_case`	`case(RxPointerLSB_rst) // synopsys parallel_case`
`2'h0 : RxByteCnt <=#Tp 2'h1;`	`2'h0 : RxByteCnt <=#Tp 2'h1;`
`2'h1 : RxByteCnt <=#Tp 2'h2;`	`2'h1 : RxByteCnt <=#Tp 2'h2;`
`2'h2 : RxByteCnt <=#Tp 2'h3;`	`2'h2 : RxByteCnt <=#Tp 2'h3;`
`2'h3 : RxByteCnt <=#Tp 2'h0;`	`2'h3 : RxByteCnt <=#Tp 2'h0;`
`endcase`	`endcase`
`else`	`else`
`if(RxValid & RxEnableWindow & RxBDReady \| LastByteIn)`	`if(RxValid & RxEnableWindow & RxReady \| LastByteIn)`
`RxByteCnt <=#Tp RxByteCnt + 1'b1;`	`RxByteCnt <=#Tp RxByteCnt + 1'b1;`
`end`	`end`


`// Indicates how many bytes are valid within the last word`	`// Indicates how many bytes are valid within the last word`
Line 1747...	Line 1762...
`always @ (posedge MRxClk or posedge Reset)`	`always @ (posedge MRxClk or posedge Reset)`
`begin`	`begin`
`if(Reset)`	`if(Reset)`
`RxDataLatched1 <=#Tp 24'h0;`	`RxDataLatched1 <=#Tp 24'h0;`
`else`	`else`
`if(RxValid & RxBDReady & ~LastByteIn)`	`if(RxValid & RxReady & ~LastByteIn)`
`if(RxStartFrm)`	`if(RxStartFrm)`
`begin`	`begin`
`case(RxPointerLSB_rst) // synopsys parallel_case`	`case(RxPointerLSB_rst) // synopsys parallel_case`
`2'h0: RxDataLatched1[31:24] <=#Tp RxData; // Big Endian Byte Ordering`	`2'h0: RxDataLatched1[31:24] <=#Tp RxData; // Big Endian Byte Ordering`
`2'h1: RxDataLatched1[23:16] <=#Tp RxData;`	`2'h1: RxDataLatched1[23:16] <=#Tp RxData;`
Line 1795...	Line 1810...
`reg WriteRxDataToFifoSync2;`	`reg WriteRxDataToFifoSync2;`
`reg WriteRxDataToFifoSync3;`	`reg WriteRxDataToFifoSync3;`


`// Indicating start of the reception process`	`// Indicating start of the reception process`
`assign SetWriteRxDataToFifo = (RxValid & RxBDReady & ~RxStartFrm & RxEnableWindow & (&RxByteCnt)) \| (RxValid & RxBDReady & RxStartFrm & (&RxPointerLSB_rst)) \| (ShiftWillEnd & LastByteIn & (&RxByteCnt));`	`assign SetWriteRxDataToFifo = (RxValid & RxReady & ~RxStartFrm & RxEnableWindow & (&RxByteCnt)) \|`
	`(RxValid & RxReady & RxStartFrm & (&RxPointerLSB_rst)) \|`
	`(ShiftWillEnd & LastByteIn & (&RxByteCnt));`

`always @ (posedge MRxClk or posedge Reset)`	`always @ (posedge MRxClk or posedge Reset)`
`begin`	`begin`
`if(Reset)`	`if(Reset)`
`WriteRxDataToFifo <=#Tp 1'b0;`	`WriteRxDataToFifo <=#Tp 1'b0;`
Line 2149...	Line 2166...
`else`	`else`
`RxE_IRQ <=#Tp 1'b0;`	`RxE_IRQ <=#Tp 1'b0;`
`end`	`end`


`assign Busy_IRQ = 1'b0;`	`// Busy Interrupt`

	`reg Busy_IRQ_rck;`
	`reg Busy_IRQ_sync1;`
	`reg Busy_IRQ_sync2;`
	`reg Busy_IRQ_sync3;`
	`reg Busy_IRQ_syncb1;`
	`reg Busy_IRQ_syncb2;`


	`always @ (posedge MRxClk or posedge Reset)`
	`begin`
	`if(Reset)`
	`Busy_IRQ_rck <=#Tp 1'b0;`
	`else`
	`if(RxValid & RxStartFrm & ~RxReady)`
	`Busy_IRQ_rck <=#Tp 1'b1;`
	`else`
	`if(Busy_IRQ_syncb2)`
	`Busy_IRQ_rck <=#Tp 1'b0;`
	`end`

	`always @ (posedge WB_CLK_I)`
	`begin`
	`Busy_IRQ_sync1 <=#Tp Busy_IRQ_rck;`
	`Busy_IRQ_sync2 <=#Tp Busy_IRQ_sync1;`
	`Busy_IRQ_sync3 <=#Tp Busy_IRQ_sync2;`
	`end`

	`always @ (posedge MRxClk)`
	`begin`
	`Busy_IRQ_syncb1 <=#Tp Busy_IRQ_sync2;`
	`Busy_IRQ_syncb2 <=#Tp Busy_IRQ_syncb1;`
	`end`

	`assign Busy_IRQ = Busy_IRQ_sync2 & ~Busy_IRQ_sync3;`



`// TX`	`// TX`
`// bit 15 ready`	`// bit 15 ready`

Browse

Tools

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_wishbone.v] - Diff between revs 164 and 166