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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_wishbone.v] - Diff between revs 226 and 227

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Line 39... Line 39...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.41  2002/10/18 15:42:09  tadejm
 
// Igor added WB burst support and repaired BUG when handling TX under-run and retry.
 
//
// Revision 1.40  2002/10/14 16:07:02  mohor
// Revision 1.40  2002/10/14 16:07:02  mohor
// TxStatus is written after last access to the TX fifo is finished (in case of abort
// TxStatus is written after last access to the TX fifo is finished (in case of abort
// or retry). TxDone is fixed.
// or retry). TxDone is fixed.
//
//
// Revision 1.39  2002/10/11 15:35:20  mohor
// Revision 1.39  2002/10/11 15:35:20  mohor
Line 231... Line 234...
    // Tx Status
    // Tx Status
    RetryCntLatched, RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost
    RetryCntLatched, RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost
 
 
    // Bist
    // Bist
`ifdef ETH_BIST
`ifdef ETH_BIST
   , trst, SO, SI, shift_DR, capture_DR, extest, tck
    ,
 
    // debug chain signals
 
    scanb_rst,      // bist scan reset
 
    scanb_clk,      // bist scan clock
 
    scanb_si,       // bist scan serial in
 
    scanb_so,       // bist scan serial out
 
    scanb_en        // bist scan shift enable
`endif
`endif
 
 
 
 
 
 
                );
                );
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output Busy_IRQ;
output Busy_IRQ;
 
 
 
 
// Bist
// Bist
`ifdef ETH_BIST
`ifdef ETH_BIST
input           trst;
input   scanb_rst;      // bist scan reset
input           shift_DR, capture_DR, tck, extest;
input   scanb_clk;      // bist scan clock
input           SI;
input   scanb_si;       // bist scan serial in
output          SO;
output  scanb_so;       // bist scan serial out
 
input   scanb_en;       // bist scan shift enable
`endif
`endif
 
 
reg TxB_IRQ;
reg TxB_IRQ;
reg TxE_IRQ;
reg TxE_IRQ;
reg RxB_IRQ;
reg RxB_IRQ;
Line 483... Line 493...
 
 
// Generic synchronous single-port RAM interface
// Generic synchronous single-port RAM interface
eth_spram_256x32 bd_ram (
eth_spram_256x32 bd_ram (
        .clk(WB_CLK_I), .rst(Reset), .ce(ram_ce), .we(ram_we), .oe(ram_oe), .addr(ram_addr), .di(ram_di), .do(ram_do)
        .clk(WB_CLK_I), .rst(Reset), .ce(ram_ce), .we(ram_we), .oe(ram_oe), .addr(ram_addr), .di(ram_di), .do(ram_do)
`ifdef ETH_BIST
`ifdef ETH_BIST
  , .trst(trst), .SO(SO), .SI(SI), .shift_DR(shift_DR), .capture_DR(capture_DR), .extest(extest), .tck(tck)
  ,
 
  .scanb_rst      (scanb_rst),
 
  .scanb_clk      (scanb_clk),
 
  .scanb_si       (scanb_si),
 
  .scanb_so       (scanb_so),
 
  .scanb_en       (scanb_en)
`endif
`endif
);
);
 
 
assign ram_ce = 1'b1;
assign ram_ce = 1'b1;
assign ram_we = BDWrite & WbEn & WbEn_q | TxStatusWrite | RxStatusWrite;
assign ram_we = BDWrite & WbEn & WbEn_q | TxStatusWrite | RxStatusWrite;

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