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https://opencores.org/ocsvn/ethmac/ethmac/trunk
[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_wishbone.v] - Diff between revs 229 and 239
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| Rev 229 |
Rev 239 |
| Line 39... |
Line 39... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.43 2002/10/18 20:53:34 mohor
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// case changed to casex.
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//
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// Revision 1.42 2002/10/18 17:04:20 tadejm
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// Revision 1.42 2002/10/18 17:04:20 tadejm
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// Changed BIST scan signals.
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// Changed BIST scan signals.
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//
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//
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// Revision 1.41 2002/10/18 15:42:09 tadejm
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// Revision 1.41 2002/10/18 15:42:09 tadejm
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// Igor added WB burst support and repaired BUG when handling TX under-run and retry.
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// Igor added WB burst support and repaired BUG when handling TX under-run and retry.
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Line 2388... |
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wire TxError;
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wire TxError;
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assign TxError = TxUnderRun | RetryLimit | LateCollLatched | CarrierSenseLost;
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assign TxError = TxUnderRun | RetryLimit | LateCollLatched | CarrierSenseLost;
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wire RxError;
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wire RxError;
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assign RxError = |RxStatusInLatched[6:0];
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// ShortFrame (RxStatusInLatched[2]) can not set an error because short frames
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// are aborted when signal r_RecSmall is set to 0 in MODER register.
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assign RxError = (|RxStatusInLatched[6:3]) | (|RxStatusInLatched[1:0]);
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// Tx Done Interrupt
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// Tx Done Interrupt
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always @ (posedge WB_CLK_I or posedge Reset)
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always @ (posedge WB_CLK_I or posedge Reset)
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begin
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begin
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if(Reset)
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if(Reset)
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