OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_wishbone.v] - Diff between revs 250 and 261

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 250 Rev 261
Line 39... Line 39...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.45  2002/11/19 17:33:34  mohor
 
// AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
 
// that a frame was received because of the promiscous mode.
 
//
// Revision 1.44  2002/11/13 22:21:40  tadejm
// Revision 1.44  2002/11/13 22:21:40  tadejm
// RxError is not generated when small frame reception is enabled and small
// RxError is not generated when small frame reception is enabled and small
// frames are received.
// frames are received.
//
//
// Revision 1.43  2002/10/18 20:53:34  mohor
// Revision 1.43  2002/10/18 20:53:34  mohor
Line 230... Line 234...
 
 
    //RX
    //RX
    MRxClk, RxData, RxValid, RxStartFrm, RxEndFrm, RxAbort,
    MRxClk, RxData, RxValid, RxStartFrm, RxEndFrm, RxAbort,
 
 
    // Register
    // Register
    r_TxEn, r_RxEn, r_TxBDNum, TX_BD_NUM_Wr,
    r_TxEn, r_RxEn, r_TxBDNum, TX_BD_NUM_Wr, r_RxFlow,
 
 
    // Interrupts
    // Interrupts
    TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ,
    TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ,
 
 
    // Rx Status
    // Rx Status
    InvalidSymbol, LatchedCrcError, RxLateCollision, ShortFrame, DribbleNibble,
    InvalidSymbol, LatchedCrcError, RxLateCollision, ShortFrame, DribbleNibble,
    ReceivedPacketTooBig, RxLength, LoadRxStatus, ReceivedPacketGood, AddressMiss,
    ReceivedPacketTooBig, RxLength, LoadRxStatus, ReceivedPacketGood, AddressMiss,
 
    ReceivedPauseFrm,
 
 
    // Tx Status
    // Tx Status
    RetryCntLatched, RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost
    RetryCntLatched, RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost
 
 
    // Bist
    // Bist
Line 302... Line 307...
input           ReceivedPacketTooBig;// Received packet is bigger than r_MaxFL
input           ReceivedPacketTooBig;// Received packet is bigger than r_MaxFL
input    [15:0] RxLength;         // Length of the incoming frame
input    [15:0] RxLength;         // Length of the incoming frame
input           LoadRxStatus;     // Rx status was loaded
input           LoadRxStatus;     // Rx status was loaded
input           ReceivedPacketGood;// Received packet's length and CRC are good
input           ReceivedPacketGood;// Received packet's length and CRC are good
input           AddressMiss;      // When a packet is received AddressMiss status is written to the Rx BD
input           AddressMiss;      // When a packet is received AddressMiss status is written to the Rx BD
 
input           r_RxFlow;
 
input           ReceivedPauseFrm;
 
 
// Tx Status signals
// Tx Status signals
input     [3:0] RetryCntLatched;  // Latched Retry Counter
input     [3:0] RetryCntLatched;  // Latched Retry Counter
input           RetryLimit;       // Retry limit reached (Retry Max value + 1 attempts were made)
input           RetryLimit;       // Retry limit reached (Retry Max value + 1 attempts were made)
input           LateCollLatched;  // Late collision occured
input           LateCollLatched;  // Late collision occured
Line 466... Line 473...
wire            SetGotData;
wire            SetGotData;
wire            GotDataEvaluate;
wire            GotDataEvaluate;
 
 
reg             WB_ACK_O;
reg             WB_ACK_O;
 
 
wire    [7:0]   RxStatusIn;
wire    [8:0]   RxStatusIn;
reg     [7:0]   RxStatusInLatched;
reg     [8:0]   RxStatusInLatched;
 
 
reg WbEn, WbEn_q;
reg WbEn, WbEn_q;
reg RxEn, RxEn_q;
reg RxEn, RxEn_q;
reg TxEn, TxEn_q;
reg TxEn, TxEn_q;
 
 
Line 1346... Line 1353...
    RxBDAddress <=#Tp TempRxBDAddress;
    RxBDAddress <=#Tp TempRxBDAddress;
end
end
 
 
wire [8:0] TxStatusInLatched = {TxUnderRun, RetryCntLatched[3:0], RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost};
wire [8:0] TxStatusInLatched = {TxUnderRun, RetryCntLatched[3:0], RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost};
 
 
assign RxBDDataIn = {LatchedRxLength, 1'b0, RxStatus, 5'h0, RxStatusInLatched};
assign RxBDDataIn = {LatchedRxLength, 1'b0, RxStatus, 4'h0, RxStatusInLatched};
assign TxBDDataIn = {LatchedTxLength, 1'b0, TxStatus, 2'h0, TxStatusInLatched};
assign TxBDDataIn = {LatchedTxLength, 1'b0, TxStatus, 2'h0, TxStatusInLatched};
 
 
 
 
// Signals used for various purposes
// Signals used for various purposes
assign TxRetryPulse   = TxRetry_wb   & ~TxRetry_wb_q;
assign TxRetryPulse   = TxRetry_wb   & ~TxRetry_wb_q;
Line 2362... Line 2369...
  if(LoadRxStatus)
  if(LoadRxStatus)
    LatchedRxLength[15:0] <=#Tp RxLength[15:0];
    LatchedRxLength[15:0] <=#Tp RxLength[15:0];
end
end
 
 
 
 
assign RxStatusIn = {AddressMiss, RxOverrun, InvalidSymbol, DribbleNibble, ReceivedPacketTooBig, ShortFrame, LatchedCrcError, RxLateCollision};
assign RxStatusIn = {ReceivedPauseFrm, AddressMiss, RxOverrun, InvalidSymbol, DribbleNibble, ReceivedPacketTooBig, ShortFrame, LatchedCrcError, RxLateCollision};
 
 
always @ (posedge MRxClk or posedge Reset)
always @ (posedge MRxClk or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    RxStatusInLatched <=#Tp 'h0;
    RxStatusInLatched <=#Tp 'h0;
Line 2433... Line 2440...
begin
begin
  if(Reset)
  if(Reset)
    RxB_IRQ <=#Tp 1'b0;
    RxB_IRQ <=#Tp 1'b0;
  else
  else
  if(RxStatusWrite & RxIRQEn)
  if(RxStatusWrite & RxIRQEn)
    RxB_IRQ <=#Tp ReceivedPacketGood & ~RxError;
    RxB_IRQ <=#Tp ReceivedPacketGood & (~RxError) & (~r_RxFlow); // When r_RxFlow is set, RXC irq is set.
  else
  else
    RxB_IRQ <=#Tp 1'b0;
    RxB_IRQ <=#Tp 1'b0;
end
end
 
 
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.