OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_wishbone.v] - Diff between revs 269 and 270

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 269 Rev 270
Line 39... Line 39...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.48  2003/01/20 12:05:26  mohor
 
// When in full duplex, transmit was sometimes blocked. Fixed.
 
//
// Revision 1.47  2002/11/22 13:26:21  mohor
// Revision 1.47  2002/11/22 13:26:21  mohor
// Registers RxStatusWrite_rck and RxStatusWriteLatched were not used
// Registers RxStatusWrite_rck and RxStatusWriteLatched were not used
// anywhere. Removed.
// anywhere. Removed.
//
//
// Revision 1.46  2002/11/22 01:57:06  mohor
// Revision 1.46  2002/11/22 01:57:06  mohor
Line 242... Line 245...
 
 
    //RX
    //RX
    MRxClk, RxData, RxValid, RxStartFrm, RxEndFrm, RxAbort,
    MRxClk, RxData, RxValid, RxStartFrm, RxEndFrm, RxAbort,
 
 
    // Register
    // Register
    r_TxEn, r_RxEn, r_TxBDNum, TX_BD_NUM_Wr, r_RxFlow,
    r_TxEn, r_RxEn, r_TxBDNum, TX_BD_NUM_Wr, r_RxFlow, r_PassAll,
 
 
    // Interrupts
    // Interrupts
    TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ,
    TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ,
 
 
    // Rx Status
    // Rx Status
Line 316... Line 319...
input    [15:0] RxLength;         // Length of the incoming frame
input    [15:0] RxLength;         // Length of the incoming frame
input           LoadRxStatus;     // Rx status was loaded
input           LoadRxStatus;     // Rx status was loaded
input           ReceivedPacketGood;// Received packet's length and CRC are good
input           ReceivedPacketGood;// Received packet's length and CRC are good
input           AddressMiss;      // When a packet is received AddressMiss status is written to the Rx BD
input           AddressMiss;      // When a packet is received AddressMiss status is written to the Rx BD
input           r_RxFlow;
input           r_RxFlow;
 
input           r_PassAll;
input           ReceivedPauseFrm;
input           ReceivedPauseFrm;
 
 
// Tx Status signals
// Tx Status signals
input     [3:0] RetryCntLatched;  // Latched Retry Counter
input     [3:0] RetryCntLatched;  // Latched Retry Counter
input           RetryLimit;       // Retry limit reached (Retry Max value + 1 attempts were made)
input           RetryLimit;       // Retry limit reached (Retry Max value + 1 attempts were made)
Line 2418... Line 2422...
always @ (posedge WB_CLK_I or posedge Reset)
always @ (posedge WB_CLK_I or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    RxB_IRQ <=#Tp 1'b0;
    RxB_IRQ <=#Tp 1'b0;
  else
  else
  if(RxStatusWrite & RxIRQEn)
  if(RxStatusWrite & RxIRQEn & ReceivedPacketGood & (~ReceivedPauseFrm | ReceivedPauseFrm & r_PassAll & (~r_RxFlow)))
    RxB_IRQ <=#Tp ReceivedPacketGood & (~RxError) & (~r_RxFlow); // When r_RxFlow is set, RXC irq is set.
    RxB_IRQ <=#Tp (~RxError);
  else
  else
    RxB_IRQ <=#Tp 1'b0;
    RxB_IRQ <=#Tp 1'b0;
end
end
 
 
 
 
Line 2431... Line 2435...
always @ (posedge WB_CLK_I or posedge Reset)
always @ (posedge WB_CLK_I or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    RxE_IRQ <=#Tp 1'b0;
    RxE_IRQ <=#Tp 1'b0;
  else
  else
  if(RxStatusWrite & RxIRQEn)
  if(RxStatusWrite & RxIRQEn & (~ReceivedPauseFrm | ReceivedPauseFrm & r_PassAll & (~r_RxFlow)))
    RxE_IRQ <=#Tp RxError;
    RxE_IRQ <=#Tp RxError;
  else
  else
    RxE_IRQ <=#Tp 1'b0;
    RxE_IRQ <=#Tp 1'b0;
end
end
 
 
Line 2477... Line 2481...
 
 
assign Busy_IRQ = Busy_IRQ_sync2 & ~Busy_IRQ_sync3;
assign Busy_IRQ = Busy_IRQ_sync2 & ~Busy_IRQ_sync3;
 
 
 
 
 
 
// TX
 
// bit 15 ready
 
// bit 14 interrupt
 
// bit 13 wrap
 
// bit 12 pad
 
// bit 11 crc
 
// bit 10 last
 
// bit 9  pause request (control frame)
 
// bit 8  TxUnderRun          
 
// bit 7-4 RetryCntLatched    
 
// bit 3  retransmittion limit
 
// bit 2  LateCollLatched        
 
// bit 1  DeferLatched        
 
// bit 0  CarrierSenseLost    
 
 
 
 
 
// RX
 
// bit 15 od rx je empty
 
// bit 14 od rx je interrupt
 
// bit 13 od rx je wrap
 
// bit 12 od rx je reserved
 
// bit 11 od rx je reserved
 
// bit 10 od rx je reserved
 
// bit 9  od rx je reserved
 
// bit 8  od rx je reserved
 
// bit 7  od rx je Miss
 
// bit 6  od rx je RxOverrun
 
// bit 5  od rx je InvalidSymbol
 
// bit 4  od rx je DribbleNibble
 
// bit 3  od rx je ReceivedPacketTooBig
 
// bit 2  od rx je ShortFrame
 
// bit 1  od rx je LatchedCrcError
 
// bit 0  od rx je RxLateCollision
 
 
 
 
 
endmodule
endmodule
 
 
 
 
 No newline at end of file
 No newline at end of file

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.