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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_wishbone.v] - Diff between revs 278 and 280

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Rev 278 Rev 280
Line 39... Line 39...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.51  2003/01/30 13:36:22  mohor
 
// A new bug (entered with previous update) fixed. When abort occured sometimes
 
// data transmission was blocked.
 
//
// Revision 1.50  2003/01/22 13:49:26  tadejm
// Revision 1.50  2003/01/22 13:49:26  tadejm
// When control packets were received, they were ignored in some cases.
// When control packets were received, they were ignored in some cases.
//
//
// Revision 1.49  2003/01/21 12:09:40  mohor
// Revision 1.49  2003/01/21 12:09:40  mohor
// When receiving normal data frame and RxFlow control was switched on, RXB
// When receiving normal data frame and RxFlow control was switched on, RXB
Line 1434... Line 1438...
always @ (posedge WB_CLK_I or posedge Reset)
always @ (posedge WB_CLK_I or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    TxAbortPacketBlocked <=#Tp 1'b0;
    TxAbortPacketBlocked <=#Tp 1'b0;
  else
  else
  if(TxAbortPacket)
 
    TxAbortPacketBlocked <=#Tp 1'b1;
 
  else
 
  if(!TxAbort_wb & TxAbort_wb_q)
  if(!TxAbort_wb & TxAbort_wb_q)
    TxAbortPacketBlocked <=#Tp 1'b0;
    TxAbortPacketBlocked <=#Tp 1'b0;
 
  else
 
  if(TxAbortPacket)
 
    TxAbortPacketBlocked <=#Tp 1'b1;
end
end
 
 
 
 
reg TxRetryPacketBlocked;
reg TxRetryPacketBlocked;
always @ (posedge WB_CLK_I or posedge Reset)
always @ (posedge WB_CLK_I or posedge Reset)
Line 1475... Line 1479...
always @ (posedge WB_CLK_I or posedge Reset)
always @ (posedge WB_CLK_I or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    TxRetryPacketBlocked <=#Tp 1'b0;
    TxRetryPacketBlocked <=#Tp 1'b0;
  else
  else
  if(TxRetryPacket)
 
    TxRetryPacketBlocked <=#Tp 1'b1;
 
  else
 
  if(!TxRetry_wb & TxRetry_wb_q)
  if(!TxRetry_wb & TxRetry_wb_q)
    TxRetryPacketBlocked <=#Tp 1'b0;
    TxRetryPacketBlocked <=#Tp 1'b0;
 
  else
 
  if(TxRetryPacket)
 
    TxRetryPacketBlocked <=#Tp 1'b1;
end
end
 
 
 
 
reg TxDonePacketBlocked;
reg TxDonePacketBlocked;
always @ (posedge WB_CLK_I or posedge Reset)
always @ (posedge WB_CLK_I or posedge Reset)
Line 1516... Line 1520...
always @ (posedge WB_CLK_I or posedge Reset)
always @ (posedge WB_CLK_I or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    TxDonePacketBlocked <=#Tp 1'b0;
    TxDonePacketBlocked <=#Tp 1'b0;
  else
  else
  if(TxDonePacket)
 
    TxDonePacketBlocked <=#Tp 1'b1;
 
  else
 
  if(!TxDone_wb & TxDone_wb_q)
  if(!TxDone_wb & TxDone_wb_q)
    TxDonePacketBlocked <=#Tp 1'b0;
    TxDonePacketBlocked <=#Tp 1'b0;
 
  else
 
  if(TxDonePacket)
 
    TxDonePacketBlocked <=#Tp 1'b1;
end
end
 
 
 
 
// Indication of the last word
// Indication of the last word
always @ (posedge MTxClk or posedge Reset)
always @ (posedge MTxClk or posedge Reset)

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