| Line 39... |
Line 39... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.52 2003/01/30 14:51:31 mohor
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// Reset has priority in some flipflops.
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//
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// Revision 1.51 2003/01/30 13:36:22 mohor
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// Revision 1.51 2003/01/30 13:36:22 mohor
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// A new bug (entered with previous update) fixed. When abort occured sometimes
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// A new bug (entered with previous update) fixed. When abort occured sometimes
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// data transmission was blocked.
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// data transmission was blocked.
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//
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//
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// Revision 1.50 2003/01/22 13:49:26 tadejm
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// Revision 1.50 2003/01/22 13:49:26 tadejm
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| Line 273... |
Line 276... |
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// Bist
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// Bist
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`ifdef ETH_BIST
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`ifdef ETH_BIST
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,
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,
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// debug chain signals
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// debug chain signals
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scanb_rst, // bist scan reset
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mbist_si_i, // bist scan serial in
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scanb_clk, // bist scan clock
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mbist_so_o, // bist scan serial out
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scanb_si, // bist scan serial in
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mbist_ctrl_i // bist chain shift control
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scanb_so, // bist scan serial out
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scanb_en // bist scan shift enable
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`endif
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`endif
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);
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);
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| Line 378... |
Line 379... |
output Busy_IRQ;
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output Busy_IRQ;
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// Bist
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// Bist
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`ifdef ETH_BIST
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`ifdef ETH_BIST
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input scanb_rst; // bist scan reset
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input mbist_si_i; // bist scan serial in
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input scanb_clk; // bist scan clock
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output mbist_so_o; // bist scan serial out
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input scanb_si; // bist scan serial in
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input [`ETH_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
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output scanb_so; // bist scan serial out
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input scanb_en; // bist scan shift enable
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`endif
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`endif
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reg TxB_IRQ;
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reg TxB_IRQ;
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reg TxE_IRQ;
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reg TxE_IRQ;
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reg RxB_IRQ;
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reg RxB_IRQ;
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| Line 534... |
Line 533... |
// Generic synchronous single-port RAM interface
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// Generic synchronous single-port RAM interface
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eth_spram_256x32 bd_ram (
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eth_spram_256x32 bd_ram (
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.clk(WB_CLK_I), .rst(Reset), .ce(ram_ce), .we(ram_we), .oe(ram_oe), .addr(ram_addr), .di(ram_di), .do(ram_do)
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.clk(WB_CLK_I), .rst(Reset), .ce(ram_ce), .we(ram_we), .oe(ram_oe), .addr(ram_addr), .di(ram_di), .do(ram_do)
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`ifdef ETH_BIST
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`ifdef ETH_BIST
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,
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,
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.scanb_rst (scanb_rst),
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.mbist_si_i (mbist_si_i),
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.scanb_clk (scanb_clk),
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.mbist_so_o (mbist_so_o),
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.scanb_si (scanb_si),
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.mbist_ctrl_i (mbist_ctrl_i)
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.scanb_so (scanb_so),
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.scanb_en (scanb_en)
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`endif
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`endif
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);
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);
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assign ram_ce = 1'b1;
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assign ram_ce = 1'b1;
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assign ram_we = BDWrite & WbEn & WbEn_q | TxStatusWrite | RxStatusWrite;
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assign ram_we = BDWrite & WbEn & WbEn_q | TxStatusWrite | RxStatusWrite;
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