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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_wishbone.v] - Diff between revs 302 and 304

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Rev 302 Rev 304
Line 39... Line 39...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.53  2003/10/17 07:46:17  markom
 
// mbist signals updated according to newest convention
 
//
// Revision 1.52  2003/01/30 14:51:31  mohor
// Revision 1.52  2003/01/30 14:51:31  mohor
// Reset has priority in some flipflops.
// Reset has priority in some flipflops.
//
//
// Revision 1.51  2003/01/30 13:36:22  mohor
// Revision 1.51  2003/01/30 13:36:22  mohor
// A new bug (entered with previous update) fixed. When abort occured sometimes
// A new bug (entered with previous update) fixed. When abort occured sometimes
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output [31:0]   WB_DAT_O;       // WISHBONE data output
output [31:0]   WB_DAT_O;       // WISHBONE data output
 
 
// WISHBONE slave
// WISHBONE slave
input   [9:2]   WB_ADR_I;       // WISHBONE address input
input   [9:2]   WB_ADR_I;       // WISHBONE address input
input           WB_WE_I;        // WISHBONE write enable input
input           WB_WE_I;        // WISHBONE write enable input
input           BDCs;           // Buffer descriptors are selected
input   [3:0]   BDCs;           // Buffer descriptors are selected
output          WB_ACK_O;       // WISHBONE acknowledge output
output          WB_ACK_O;       // WISHBONE acknowledge output
 
 
// WISHBONE master
// WISHBONE master
output  [31:0]  m_wb_adr_o;     // 
output  [31:0]  m_wb_adr_o;     // 
output   [3:0]  m_wb_sel_o;     // 
output   [3:0]  m_wb_sel_o;     // 
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reg             RxAbortLatched;
reg             RxAbortLatched;
 
 
reg             ShiftEnded;
reg             ShiftEnded;
reg             RxOverrun;
reg             RxOverrun;
 
 
reg             BDWrite;                    // BD Write Enable for access from WISHBONE side
reg     [3:0]   BDWrite;                    // BD Write Enable for access from WISHBONE side
reg             BDRead;                     // BD Read access from WISHBONE side
reg             BDRead;                     // BD Read access from WISHBONE side
wire   [31:0]   RxBDDataIn;                 // Rx BD data in
wire   [31:0]   RxBDDataIn;                 // Rx BD data in
wire   [31:0]   TxBDDataIn;                 // Tx BD data in
wire   [31:0]   TxBDDataIn;                 // Tx BD data in
 
 
reg             TxEndFrm_wb;
reg             TxEndFrm_wb;
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reg WbEn, WbEn_q;
reg WbEn, WbEn_q;
reg RxEn, RxEn_q;
reg RxEn, RxEn_q;
reg TxEn, TxEn_q;
reg TxEn, TxEn_q;
 
 
wire ram_ce;
wire ram_ce;
wire ram_we;
wire [3:0]  ram_we;
wire ram_oe;
wire ram_oe;
reg [7:0]   ram_addr;
reg [7:0]   ram_addr;
reg [31:0]  ram_di;
reg [31:0]  ram_di;
wire [31:0] ram_do;
wire [31:0] ram_do;
 
 
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`endif
`endif
 
 
 
 
always @ (posedge WB_CLK_I)
always @ (posedge WB_CLK_I)
begin
begin
  WB_ACK_O <=#Tp BDWrite & WbEn & WbEn_q | BDRead & WbEn & ~WbEn_q;
  WB_ACK_O <=#Tp (|BDWrite) & WbEn & WbEn_q | BDRead & WbEn & ~WbEn_q;
end
end
 
 
assign WB_DAT_O = ram_do;
assign WB_DAT_O = ram_do;
 
 
// Generic synchronous single-port RAM interface
// Generic synchronous single-port RAM interface
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  .mbist_ctrl_i       (mbist_ctrl_i)
  .mbist_ctrl_i       (mbist_ctrl_i)
`endif
`endif
);
);
 
 
assign ram_ce = 1'b1;
assign ram_ce = 1'b1;
assign ram_we = BDWrite & WbEn & WbEn_q | TxStatusWrite | RxStatusWrite;
assign ram_we = (BDWrite & {4{(WbEn & WbEn_q)}}) | {4{(TxStatusWrite | RxStatusWrite)}};
assign ram_oe = BDRead & WbEn & WbEn_q | TxEn & TxEn_q & (TxBDRead | TxPointerRead) | RxEn & RxEn_q & (RxBDRead | RxPointerRead);
assign ram_oe = BDRead & WbEn & WbEn_q | TxEn & TxEn_q & (TxBDRead | TxPointerRead) | RxEn & RxEn_q & (RxBDRead | RxPointerRead);
 
 
 
 
always @ (posedge WB_CLK_I or posedge Reset)
always @ (posedge WB_CLK_I or posedge Reset)
begin
begin
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            WbEn <=#Tp 1'b1;  // RxEn access stage and r_TxEn is disabled
            WbEn <=#Tp 1'b1;  // RxEn access stage and r_TxEn is disabled
            RxEn <=#Tp 1'b0;
            RxEn <=#Tp 1'b0;
            TxEn <=#Tp 1'b0;
            TxEn <=#Tp 1'b0;
            ram_addr <=#Tp WB_ADR_I[9:2];
            ram_addr <=#Tp WB_ADR_I[9:2];
            ram_di <=#Tp WB_DAT_I;
            ram_di <=#Tp WB_DAT_I;
            BDWrite <=#Tp BDCs & WB_WE_I;
            BDWrite <=#Tp BDCs[3:0] & {4{WB_WE_I}};
            BDRead <=#Tp BDCs & ~WB_WE_I;
            BDRead <=#Tp (|BDCs) & ~WB_WE_I;
          end
          end
        5'b010_01, 5'b010_11 :
        5'b010_01, 5'b010_11 :
          begin
          begin
            WbEn <=#Tp 1'b0;
            WbEn <=#Tp 1'b0;
            RxEn <=#Tp 1'b0;
            RxEn <=#Tp 1'b0;
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            WbEn <=#Tp 1'b1;  // TxEn access stage (we always go to wb access stage)
            WbEn <=#Tp 1'b1;  // TxEn access stage (we always go to wb access stage)
            RxEn <=#Tp 1'b0;
            RxEn <=#Tp 1'b0;
            TxEn <=#Tp 1'b0;
            TxEn <=#Tp 1'b0;
            ram_addr <=#Tp WB_ADR_I[9:2];
            ram_addr <=#Tp WB_ADR_I[9:2];
            ram_di <=#Tp WB_DAT_I;
            ram_di <=#Tp WB_DAT_I;
            BDWrite <=#Tp BDCs & WB_WE_I;
            BDWrite <=#Tp BDCs[3:0] & {4{WB_WE_I}};
            BDRead <=#Tp BDCs & ~WB_WE_I;
            BDRead <=#Tp (|BDCs) & ~WB_WE_I;
          end
          end
        5'b100_00 :
        5'b100_00 :
          begin
          begin
            WbEn <=#Tp 1'b0;  // WbEn access stage and there is no need for other stages. WbEn needs to be switched off for a bit
            WbEn <=#Tp 1'b0;  // WbEn access stage and there is no need for other stages. WbEn needs to be switched off for a bit
          end
          end
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            WbEn <=#Tp 1'b1;  // Idle state. We go to WbEn access stage.
            WbEn <=#Tp 1'b1;  // Idle state. We go to WbEn access stage.
            RxEn <=#Tp 1'b0;
            RxEn <=#Tp 1'b0;
            TxEn <=#Tp 1'b0;
            TxEn <=#Tp 1'b0;
            ram_addr <=#Tp WB_ADR_I[9:2];
            ram_addr <=#Tp WB_ADR_I[9:2];
            ram_di <=#Tp WB_DAT_I;
            ram_di <=#Tp WB_DAT_I;
            BDWrite <=#Tp BDCs & WB_WE_I;
            BDWrite <=#Tp BDCs[3:0] & {4{WB_WE_I}};
            BDRead <=#Tp BDCs & ~WB_WE_I;
            BDRead <=#Tp (|BDCs) & ~WB_WE_I;
          end
          end
      endcase
      endcase
    end
    end
end
end
 
 
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// Latching Rx buffer descriptor address
// Latching Rx buffer descriptor address
always @ (posedge WB_CLK_I or posedge Reset)
always @ (posedge WB_CLK_I or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    RxBDAddress <=#Tp `ETH_TX_BD_NUM_DEF<<1;
    RxBDAddress <=#Tp `ETH_TX_BD_NUM_DEF_0 << 1;
  else
  else
  if(TX_BD_NUM_Wr)                        // When r_TxBDNum is updated, RxBDAddress is also
  if(TX_BD_NUM_Wr)                        // When r_TxBDNum is updated, RxBDAddress is also
    RxBDAddress <=#Tp WB_DAT_I[7:0]<<1;
    RxBDAddress <=#Tp WB_DAT_I[7:0]<<1;
  else
  else
  if(RxStatusWrite)
  if(RxStatusWrite)

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