| Line 306... |
Line 306... |
|
|
|
|
);
|
);
|
|
|
|
|
parameter Tp = 1;
|
|
parameter TX_FIFO_DATA_WIDTH = `ETH_TX_FIFO_DATA_WIDTH;
|
parameter TX_FIFO_DATA_WIDTH = `ETH_TX_FIFO_DATA_WIDTH;
|
parameter TX_FIFO_DEPTH = `ETH_TX_FIFO_DEPTH;
|
parameter TX_FIFO_DEPTH = `ETH_TX_FIFO_DEPTH;
|
parameter TX_FIFO_CNT_WIDTH = `ETH_TX_FIFO_CNT_WIDTH;
|
parameter TX_FIFO_CNT_WIDTH = `ETH_TX_FIFO_CNT_WIDTH;
|
parameter RX_FIFO_DATA_WIDTH = `ETH_RX_FIFO_DATA_WIDTH;
|
parameter RX_FIFO_DATA_WIDTH = `ETH_RX_FIFO_DATA_WIDTH;
|
parameter RX_FIFO_DEPTH = `ETH_RX_FIFO_DEPTH;
|
parameter RX_FIFO_DEPTH = `ETH_RX_FIFO_DEPTH;
|
| Line 555... |
Line 554... |
|
|
assign m_wb_stb_o = m_wb_cyc_o;
|
assign m_wb_stb_o = m_wb_cyc_o;
|
|
|
always @ (posedge WB_CLK_I)
|
always @ (posedge WB_CLK_I)
|
begin
|
begin
|
WB_ACK_O <=#Tp (|BDWrite) & WbEn & WbEn_q | BDRead & WbEn & ~WbEn_q;
|
WB_ACK_O <= (|BDWrite) & WbEn & WbEn_q | BDRead & WbEn & ~WbEn_q;
|
end
|
end
|
|
|
assign WB_DAT_O = ram_do;
|
assign WB_DAT_O = ram_do;
|
|
|
// Generic synchronous single-port RAM interface
|
// Generic synchronous single-port RAM interface
|
| Line 579... |
Line 578... |
|
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
TxEn_needed <=#Tp 1'b0;
|
TxEn_needed <= 1'b0;
|
else
|
else
|
if(~TxBDReady & r_TxEn & WbEn & ~WbEn_q)
|
if(~TxBDReady & r_TxEn & WbEn & ~WbEn_q)
|
TxEn_needed <=#Tp 1'b1;
|
TxEn_needed <= 1'b1;
|
else
|
else
|
if(TxPointerRead & TxEn & TxEn_q)
|
if(TxPointerRead & TxEn & TxEn_q)
|
TxEn_needed <=#Tp 1'b0;
|
TxEn_needed <= 1'b0;
|
end
|
end
|
|
|
// Enabling access to the RAM for three devices.
|
// Enabling access to the RAM for three devices.
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
begin
|
begin
|
WbEn <=#Tp 1'b1;
|
WbEn <= 1'b1;
|
RxEn <=#Tp 1'b0;
|
RxEn <= 1'b0;
|
TxEn <=#Tp 1'b0;
|
TxEn <= 1'b0;
|
ram_addr <=#Tp 8'h0;
|
ram_addr <= 8'h0;
|
ram_di <=#Tp 32'h0;
|
ram_di <= 32'h0;
|
BDRead <=#Tp 1'b0;
|
BDRead <= 1'b0;
|
BDWrite <=#Tp 1'b0;
|
BDWrite <= 1'b0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
// Switching between three stages depends on enable signals
|
// Switching between three stages depends on enable signals
|
case ({WbEn_q, RxEn_q, TxEn_q, RxEn_needed, TxEn_needed}) // synopsys parallel_case
|
case ({WbEn_q, RxEn_q, TxEn_q, RxEn_needed, TxEn_needed}) // synopsys parallel_case
|
5'b100_10, 5'b100_11 :
|
5'b100_10, 5'b100_11 :
|
begin
|
begin
|
WbEn <=#Tp 1'b0;
|
WbEn <= 1'b0;
|
RxEn <=#Tp 1'b1; // wb access stage and r_RxEn is enabled
|
RxEn <= 1'b1; // wb access stage and r_RxEn is enabled
|
TxEn <=#Tp 1'b0;
|
TxEn <= 1'b0;
|
ram_addr <=#Tp {RxBDAddress, RxPointerRead};
|
ram_addr <= {RxBDAddress, RxPointerRead};
|
ram_di <=#Tp RxBDDataIn;
|
ram_di <= RxBDDataIn;
|
end
|
end
|
5'b100_01 :
|
5'b100_01 :
|
begin
|
begin
|
WbEn <=#Tp 1'b0;
|
WbEn <= 1'b0;
|
RxEn <=#Tp 1'b0;
|
RxEn <= 1'b0;
|
TxEn <=#Tp 1'b1; // wb access stage, r_RxEn is disabled but r_TxEn is enabled
|
TxEn <= 1'b1; // wb access stage, r_RxEn is disabled but r_TxEn is enabled
|
ram_addr <=#Tp {TxBDAddress, TxPointerRead};
|
ram_addr <= {TxBDAddress, TxPointerRead};
|
ram_di <=#Tp TxBDDataIn;
|
ram_di <= TxBDDataIn;
|
end
|
end
|
5'b010_00, 5'b010_10 :
|
5'b010_00, 5'b010_10 :
|
begin
|
begin
|
WbEn <=#Tp 1'b1; // RxEn access stage and r_TxEn is disabled
|
WbEn <= 1'b1; // RxEn access stage and r_TxEn is disabled
|
RxEn <=#Tp 1'b0;
|
RxEn <= 1'b0;
|
TxEn <=#Tp 1'b0;
|
TxEn <= 1'b0;
|
ram_addr <=#Tp WB_ADR_I[9:2];
|
ram_addr <= WB_ADR_I[9:2];
|
ram_di <=#Tp WB_DAT_I;
|
ram_di <= WB_DAT_I;
|
BDWrite <=#Tp BDCs[3:0] & {4{WB_WE_I}};
|
BDWrite <= BDCs[3:0] & {4{WB_WE_I}};
|
BDRead <=#Tp (|BDCs) & ~WB_WE_I;
|
BDRead <= (|BDCs) & ~WB_WE_I;
|
end
|
end
|
5'b010_01, 5'b010_11 :
|
5'b010_01, 5'b010_11 :
|
begin
|
begin
|
WbEn <=#Tp 1'b0;
|
WbEn <= 1'b0;
|
RxEn <=#Tp 1'b0;
|
RxEn <= 1'b0;
|
TxEn <=#Tp 1'b1; // RxEn access stage and r_TxEn is enabled
|
TxEn <= 1'b1; // RxEn access stage and r_TxEn is enabled
|
ram_addr <=#Tp {TxBDAddress, TxPointerRead};
|
ram_addr <= {TxBDAddress, TxPointerRead};
|
ram_di <=#Tp TxBDDataIn;
|
ram_di <= TxBDDataIn;
|
end
|
end
|
5'b001_00, 5'b001_01, 5'b001_10, 5'b001_11 :
|
5'b001_00, 5'b001_01, 5'b001_10, 5'b001_11 :
|
begin
|
begin
|
WbEn <=#Tp 1'b1; // TxEn access stage (we always go to wb access stage)
|
WbEn <= 1'b1; // TxEn access stage (we always go to wb access stage)
|
RxEn <=#Tp 1'b0;
|
RxEn <= 1'b0;
|
TxEn <=#Tp 1'b0;
|
TxEn <= 1'b0;
|
ram_addr <=#Tp WB_ADR_I[9:2];
|
ram_addr <= WB_ADR_I[9:2];
|
ram_di <=#Tp WB_DAT_I;
|
ram_di <= WB_DAT_I;
|
BDWrite <=#Tp BDCs[3:0] & {4{WB_WE_I}};
|
BDWrite <= BDCs[3:0] & {4{WB_WE_I}};
|
BDRead <=#Tp (|BDCs) & ~WB_WE_I;
|
BDRead <= (|BDCs) & ~WB_WE_I;
|
end
|
end
|
5'b100_00 :
|
5'b100_00 :
|
begin
|
begin
|
WbEn <=#Tp 1'b0; // WbEn access stage and there is no need for other stages. WbEn needs to be switched off for a bit
|
WbEn <= 1'b0; // WbEn access stage and there is no need for other stages. WbEn needs to be switched off for a bit
|
end
|
end
|
5'b000_00 :
|
5'b000_00 :
|
begin
|
begin
|
WbEn <=#Tp 1'b1; // Idle state. We go to WbEn access stage.
|
WbEn <= 1'b1; // Idle state. We go to WbEn access stage.
|
RxEn <=#Tp 1'b0;
|
RxEn <= 1'b0;
|
TxEn <=#Tp 1'b0;
|
TxEn <= 1'b0;
|
ram_addr <=#Tp WB_ADR_I[9:2];
|
ram_addr <= WB_ADR_I[9:2];
|
ram_di <=#Tp WB_DAT_I;
|
ram_di <= WB_DAT_I;
|
BDWrite <=#Tp BDCs[3:0] & {4{WB_WE_I}};
|
BDWrite <= BDCs[3:0] & {4{WB_WE_I}};
|
BDRead <=#Tp (|BDCs) & ~WB_WE_I;
|
BDRead <= (|BDCs) & ~WB_WE_I;
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
|
|
| Line 673... |
Line 672... |
// Delayed stage signals
|
// Delayed stage signals
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
begin
|
begin
|
WbEn_q <=#Tp 1'b0;
|
WbEn_q <= 1'b0;
|
RxEn_q <=#Tp 1'b0;
|
RxEn_q <= 1'b0;
|
TxEn_q <=#Tp 1'b0;
|
TxEn_q <= 1'b0;
|
r_TxEn_q <=#Tp 1'b0;
|
r_TxEn_q <= 1'b0;
|
r_RxEn_q <=#Tp 1'b0;
|
r_RxEn_q <= 1'b0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
WbEn_q <=#Tp WbEn;
|
WbEn_q <= WbEn;
|
RxEn_q <=#Tp RxEn;
|
RxEn_q <= RxEn;
|
TxEn_q <=#Tp TxEn;
|
TxEn_q <= TxEn;
|
r_TxEn_q <=#Tp r_TxEn;
|
r_TxEn_q <= r_TxEn;
|
r_RxEn_q <=#Tp r_RxEn;
|
r_RxEn_q <= r_RxEn;
|
end
|
end
|
end
|
end
|
|
|
// Changes for tx occur every second clock. Flop is used for this manner.
|
// Changes for tx occur every second clock. Flop is used for this manner.
|
always @ (posedge MTxClk or posedge Reset)
|
always @ (posedge MTxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
Flop <=#Tp 1'b0;
|
Flop <= 1'b0;
|
else
|
else
|
if(TxDone | TxAbort | TxRetry_q)
|
if(TxDone | TxAbort | TxRetry_q)
|
Flop <=#Tp 1'b0;
|
Flop <= 1'b0;
|
else
|
else
|
if(TxUsedData)
|
if(TxUsedData)
|
Flop <=#Tp ~Flop;
|
Flop <= ~Flop;
|
end
|
end
|
|
|
wire ResetTxBDReady;
|
wire ResetTxBDReady;
|
assign ResetTxBDReady = TxDonePulse | TxAbortPulse | TxRetryPulse;
|
assign ResetTxBDReady = TxDonePulse | TxAbortPulse | TxRetryPulse;
|
|
|
// Latching READY status of the Tx buffer descriptor
|
// Latching READY status of the Tx buffer descriptor
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
TxBDReady <=#Tp 1'b0;
|
TxBDReady <= 1'b0;
|
else
|
else
|
if(TxEn & TxEn_q & TxBDRead)
|
if(TxEn & TxEn_q & TxBDRead)
|
TxBDReady <=#Tp ram_do[15] & (ram_do[31:16] > 4); // TxBDReady is sampled only once at the beginning.
|
TxBDReady <= ram_do[15] & (ram_do[31:16] > 4); // TxBDReady is sampled only once at the beginning.
|
else // Only packets larger then 4 bytes are transmitted.
|
else // Only packets larger then 4 bytes are transmitted.
|
if(ResetTxBDReady)
|
if(ResetTxBDReady)
|
TxBDReady <=#Tp 1'b0;
|
TxBDReady <= 1'b0;
|
end
|
end
|
|
|
|
|
// Reading the Tx buffer descriptor
|
// Reading the Tx buffer descriptor
|
assign StartTxBDRead = (TxRetryPacket_NotCleared | TxStatusWrite) & ~BlockingTxBDRead & ~TxBDReady;
|
assign StartTxBDRead = (TxRetryPacket_NotCleared | TxStatusWrite) & ~BlockingTxBDRead & ~TxBDReady;
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
TxBDRead <=#Tp 1'b1;
|
TxBDRead <= 1'b1;
|
else
|
else
|
if(StartTxBDRead)
|
if(StartTxBDRead)
|
TxBDRead <=#Tp 1'b1;
|
TxBDRead <= 1'b1;
|
else
|
else
|
if(TxBDReady)
|
if(TxBDReady)
|
TxBDRead <=#Tp 1'b0;
|
TxBDRead <= 1'b0;
|
end
|
end
|
|
|
|
|
// Reading Tx BD pointer
|
// Reading Tx BD pointer
|
assign StartTxPointerRead = TxBDRead & TxBDReady;
|
assign StartTxPointerRead = TxBDRead & TxBDReady;
|
|
|
// Reading Tx BD Pointer
|
// Reading Tx BD Pointer
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
TxPointerRead <=#Tp 1'b0;
|
TxPointerRead <= 1'b0;
|
else
|
else
|
if(StartTxPointerRead)
|
if(StartTxPointerRead)
|
TxPointerRead <=#Tp 1'b1;
|
TxPointerRead <= 1'b1;
|
else
|
else
|
if(TxEn_q)
|
if(TxEn_q)
|
TxPointerRead <=#Tp 1'b0;
|
TxPointerRead <= 1'b0;
|
end
|
end
|
|
|
|
|
// Writing status back to the Tx buffer descriptor
|
// Writing status back to the Tx buffer descriptor
|
assign TxStatusWrite = (TxDonePacket_NotCleared | TxAbortPacket_NotCleared) & TxEn & TxEn_q & ~BlockingTxStatusWrite;
|
assign TxStatusWrite = (TxDonePacket_NotCleared | TxAbortPacket_NotCleared) & TxEn & TxEn_q & ~BlockingTxStatusWrite;
|
| Line 761... |
Line 760... |
|
|
// Status writing must occur only once. Meanwhile it is blocked.
|
// Status writing must occur only once. Meanwhile it is blocked.
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
BlockingTxStatusWrite <=#Tp 1'b0;
|
BlockingTxStatusWrite <= 1'b0;
|
else
|
else
|
if(~TxDone_wb & ~TxAbort_wb)
|
if(~TxDone_wb & ~TxAbort_wb)
|
BlockingTxStatusWrite <=#Tp 1'b0;
|
BlockingTxStatusWrite <= 1'b0;
|
else
|
else
|
if(TxStatusWrite)
|
if(TxStatusWrite)
|
BlockingTxStatusWrite <=#Tp 1'b1;
|
BlockingTxStatusWrite <= 1'b1;
|
end
|
end
|
|
|
|
|
reg BlockingTxStatusWrite_sync1;
|
reg BlockingTxStatusWrite_sync1;
|
reg BlockingTxStatusWrite_sync2;
|
reg BlockingTxStatusWrite_sync2;
|
| Line 779... |
Line 778... |
|
|
// Synchronizing BlockingTxStatusWrite to MTxClk
|
// Synchronizing BlockingTxStatusWrite to MTxClk
|
always @ (posedge MTxClk or posedge Reset)
|
always @ (posedge MTxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
BlockingTxStatusWrite_sync1 <=#Tp 1'b0;
|
BlockingTxStatusWrite_sync1 <= 1'b0;
|
else
|
else
|
BlockingTxStatusWrite_sync1 <=#Tp BlockingTxStatusWrite;
|
BlockingTxStatusWrite_sync1 <= BlockingTxStatusWrite;
|
end
|
end
|
|
|
// Synchronizing BlockingTxStatusWrite to MTxClk
|
// Synchronizing BlockingTxStatusWrite to MTxClk
|
always @ (posedge MTxClk or posedge Reset)
|
always @ (posedge MTxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
BlockingTxStatusWrite_sync2 <=#Tp 1'b0;
|
BlockingTxStatusWrite_sync2 <= 1'b0;
|
else
|
else
|
BlockingTxStatusWrite_sync2 <=#Tp BlockingTxStatusWrite_sync1;
|
BlockingTxStatusWrite_sync2 <= BlockingTxStatusWrite_sync1;
|
end
|
end
|
|
|
// Synchronizing BlockingTxStatusWrite to MTxClk
|
// Synchronizing BlockingTxStatusWrite to MTxClk
|
always @ (posedge MTxClk or posedge Reset)
|
always @ (posedge MTxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
BlockingTxStatusWrite_sync3 <=#Tp 1'b0;
|
BlockingTxStatusWrite_sync3 <= 1'b0;
|
else
|
else
|
BlockingTxStatusWrite_sync3 <=#Tp BlockingTxStatusWrite_sync2;
|
BlockingTxStatusWrite_sync3 <= BlockingTxStatusWrite_sync2;
|
end
|
end
|
|
|
assign RstDeferLatched = BlockingTxStatusWrite_sync2 & ~BlockingTxStatusWrite_sync3;
|
assign RstDeferLatched = BlockingTxStatusWrite_sync2 & ~BlockingTxStatusWrite_sync3;
|
|
|
// TxBDRead state is activated only once.
|
// TxBDRead state is activated only once.
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
BlockingTxBDRead <=#Tp 1'b0;
|
BlockingTxBDRead <= 1'b0;
|
else
|
else
|
if(StartTxBDRead)
|
if(StartTxBDRead)
|
BlockingTxBDRead <=#Tp 1'b1;
|
BlockingTxBDRead <= 1'b1;
|
else
|
else
|
if(~StartTxBDRead & ~TxBDReady)
|
if(~StartTxBDRead & ~TxBDReady)
|
BlockingTxBDRead <=#Tp 1'b0;
|
BlockingTxBDRead <= 1'b0;
|
end
|
end
|
|
|
|
|
// Latching status from the tx buffer descriptor
|
// Latching status from the tx buffer descriptor
|
// Data is avaliable one cycle after the access is started (at that time signal TxEn is not active)
|
// Data is avaliable one cycle after the access is started (at that time signal TxEn is not active)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
TxStatus <=#Tp 4'h0;
|
TxStatus <= 4'h0;
|
else
|
else
|
if(TxEn & TxEn_q & TxBDRead)
|
if(TxEn & TxEn_q & TxBDRead)
|
TxStatus <=#Tp ram_do[14:11];
|
TxStatus <= ram_do[14:11];
|
end
|
end
|
|
|
reg ReadTxDataFromMemory;
|
reg ReadTxDataFromMemory;
|
wire WriteRxDataToMemory;
|
wire WriteRxDataToMemory;
|
|
|
| Line 859... |
Line 858... |
|
|
//Latching length from the buffer descriptor;
|
//Latching length from the buffer descriptor;
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
TxLength <=#Tp 16'h0;
|
TxLength <= 16'h0;
|
else
|
else
|
if(TxEn & TxEn_q & TxBDRead)
|
if(TxEn & TxEn_q & TxBDRead)
|
TxLength <=#Tp ram_do[31:16];
|
TxLength <= ram_do[31:16];
|
else
|
else
|
if(MasterWbTX & m_wb_ack_i)
|
if(MasterWbTX & m_wb_ack_i)
|
begin
|
begin
|
if(TxLengthLt4)
|
if(TxLengthLt4)
|
TxLength <=#Tp 16'h0;
|
TxLength <= 16'h0;
|
else
|
else
|
if(TxPointerLSB_rst==2'h0)
|
if(TxPointerLSB_rst==2'h0)
|
TxLength <=#Tp TxLength - 3'h4; // Length is subtracted at the data request
|
TxLength <= TxLength - 3'h4; // Length is subtracted at the data request
|
else
|
else
|
if(TxPointerLSB_rst==2'h1)
|
if(TxPointerLSB_rst==2'h1)
|
TxLength <=#Tp TxLength - 3'h3; // Length is subtracted at the data request
|
TxLength <= TxLength - 3'h3; // Length is subtracted at the data request
|
else
|
else
|
if(TxPointerLSB_rst==2'h2)
|
if(TxPointerLSB_rst==2'h2)
|
TxLength <=#Tp TxLength - 3'h2; // Length is subtracted at the data request
|
TxLength <= TxLength - 3'h2; // Length is subtracted at the data request
|
else
|
else
|
if(TxPointerLSB_rst==2'h3)
|
if(TxPointerLSB_rst==2'h3)
|
TxLength <=#Tp TxLength - 3'h1; // Length is subtracted at the data request
|
TxLength <= TxLength - 3'h1; // Length is subtracted at the data request
|
end
|
end
|
end
|
end
|
|
|
|
|
|
|
//Latching length from the buffer descriptor;
|
//Latching length from the buffer descriptor;
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
LatchedTxLength <=#Tp 16'h0;
|
LatchedTxLength <= 16'h0;
|
else
|
else
|
if(TxEn & TxEn_q & TxBDRead)
|
if(TxEn & TxEn_q & TxBDRead)
|
LatchedTxLength <=#Tp ram_do[31:16];
|
LatchedTxLength <= ram_do[31:16];
|
end
|
end
|
|
|
assign TxLengthEq0 = TxLength == 0;
|
assign TxLengthEq0 = TxLength == 0;
|
assign TxLengthLt4 = TxLength < 4;
|
assign TxLengthLt4 = TxLength < 4;
|
|
|
| Line 907... |
Line 906... |
// Latching Tx buffer pointer from buffer descriptor. Only 30 MSB bits are latched
|
// Latching Tx buffer pointer from buffer descriptor. Only 30 MSB bits are latched
|
// because TxPointerMSB is only used for word-aligned accesses.
|
// because TxPointerMSB is only used for word-aligned accesses.
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
TxPointerMSB <=#Tp 30'h0;
|
TxPointerMSB <= 30'h0;
|
else
|
else
|
if(TxEn & TxEn_q & TxPointerRead)
|
if(TxEn & TxEn_q & TxPointerRead)
|
TxPointerMSB <=#Tp ram_do[31:2];
|
TxPointerMSB <= ram_do[31:2];
|
else
|
else
|
if(IncrTxPointer & ~BlockingIncrementTxPointer)
|
if(IncrTxPointer & ~BlockingIncrementTxPointer)
|
TxPointerMSB <=#Tp TxPointerMSB + 1'b1; // TxPointer is word-aligned
|
TxPointerMSB <= TxPointerMSB + 1'b1; // TxPointer is word-aligned
|
end
|
end
|
|
|
|
|
// Latching 2 MSB bits of the buffer descriptor. Since word accesses are performed,
|
// Latching 2 MSB bits of the buffer descriptor. Since word accesses are performed,
|
// valid data does not necesserly start at byte 0 (could be byte 0, 1, 2 or 3). This
|
// valid data does not necesserly start at byte 0 (could be byte 0, 1, 2 or 3). This
|
// signals are used for proper selection of the start byte (TxData and TxByteCnt) are
|
// signals are used for proper selection of the start byte (TxData and TxByteCnt) are
|
// set by this two bits.
|
// set by this two bits.
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
TxPointerLSB[1:0] <=#Tp 0;
|
TxPointerLSB[1:0] <= 0;
|
else
|
else
|
if(TxEn & TxEn_q & TxPointerRead)
|
if(TxEn & TxEn_q & TxPointerRead)
|
TxPointerLSB[1:0] <=#Tp ram_do[1:0];
|
TxPointerLSB[1:0] <= ram_do[1:0];
|
end
|
end
|
|
|
|
|
// Latching 2 MSB bits of the buffer descriptor.
|
// Latching 2 MSB bits of the buffer descriptor.
|
// After the read access, TxLength needs to be decremented for the number of the valid
|
// After the read access, TxLength needs to be decremented for the number of the valid
|
// bytes (1 to 4 bytes are valid in the first word). After the first read all bytes are
|
// bytes (1 to 4 bytes are valid in the first word). After the first read all bytes are
|
// valid so this two bits are reset to zero.
|
// valid so this two bits are reset to zero.
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
TxPointerLSB_rst[1:0] <=#Tp 0;
|
TxPointerLSB_rst[1:0] <= 0;
|
else
|
else
|
if(TxEn & TxEn_q & TxPointerRead)
|
if(TxEn & TxEn_q & TxPointerRead)
|
TxPointerLSB_rst[1:0] <=#Tp ram_do[1:0];
|
TxPointerLSB_rst[1:0] <= ram_do[1:0];
|
else
|
else
|
if(MasterWbTX & m_wb_ack_i) // After first access pointer is word alligned
|
if(MasterWbTX & m_wb_ack_i) // After first access pointer is word alligned
|
TxPointerLSB_rst[1:0] <=#Tp 0;
|
TxPointerLSB_rst[1:0] <= 0;
|
end
|
end
|
|
|
|
|
reg [3:0] RxByteSel;
|
reg [3:0] RxByteSel;
|
wire MasterAccessFinished;
|
wire MasterAccessFinished;
|
|
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
BlockingIncrementTxPointer <=#Tp 0;
|
BlockingIncrementTxPointer <= 0;
|
else
|
else
|
if(MasterAccessFinished)
|
if(MasterAccessFinished)
|
BlockingIncrementTxPointer <=#Tp 0;
|
BlockingIncrementTxPointer <= 0;
|
else
|
else
|
if(IncrTxPointer)
|
if(IncrTxPointer)
|
BlockingIncrementTxPointer <=#Tp 1'b1;
|
BlockingIncrementTxPointer <= 1'b1;
|
end
|
end
|
|
|
|
|
wire TxBufferAlmostFull;
|
wire TxBufferAlmostFull;
|
wire TxBufferFull;
|
wire TxBufferFull;
|
| Line 978... |
Line 977... |
assign SetReadTxDataFromMemory = TxEn & TxEn_q & TxPointerRead;
|
assign SetReadTxDataFromMemory = TxEn & TxEn_q & TxPointerRead;
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
ReadTxDataFromMemory <=#Tp 1'b0;
|
ReadTxDataFromMemory <= 1'b0;
|
else
|
else
|
if(TxLengthEq0 | TxAbortPulse | TxRetryPulse)
|
if(TxLengthEq0 | TxAbortPulse | TxRetryPulse)
|
ReadTxDataFromMemory <=#Tp 1'b0;
|
ReadTxDataFromMemory <= 1'b0;
|
else
|
else
|
if(SetReadTxDataFromMemory)
|
if(SetReadTxDataFromMemory)
|
ReadTxDataFromMemory <=#Tp 1'b1;
|
ReadTxDataFromMemory <= 1'b1;
|
end
|
end
|
|
|
reg tx_burst_en;
|
reg tx_burst_en;
|
reg rx_burst_en;
|
reg rx_burst_en;
|
|
|
| Line 999... |
Line 998... |
wire ReadTxDataFromFifo_wb;
|
wire ReadTxDataFromFifo_wb;
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
BlockReadTxDataFromMemory <=#Tp 1'b0;
|
BlockReadTxDataFromMemory <= 1'b0;
|
else
|
else
|
if((TxBufferAlmostFull | TxLength <= 4)& MasterWbTX & (~cyc_cleared) & (!(TxAbortPacket_NotCleared | TxRetryPacket_NotCleared)))
|
if((TxBufferAlmostFull | TxLength <= 4)& MasterWbTX & (~cyc_cleared) & (!(TxAbortPacket_NotCleared | TxRetryPacket_NotCleared)))
|
BlockReadTxDataFromMemory <=#Tp 1'b1;
|
BlockReadTxDataFromMemory <= 1'b1;
|
else
|
else
|
if(ReadTxDataFromFifo_wb | TxDonePacket | TxAbortPacket | TxRetryPacket)
|
if(ReadTxDataFromFifo_wb | TxDonePacket | TxAbortPacket | TxRetryPacket)
|
BlockReadTxDataFromMemory <=#Tp 1'b0;
|
BlockReadTxDataFromMemory <= 1'b0;
|
end
|
end
|
|
|
|
|
assign MasterAccessFinished = m_wb_ack_i | m_wb_err_i;
|
assign MasterAccessFinished = m_wb_ack_i | m_wb_err_i;
|
wire [TX_FIFO_CNT_WIDTH-1:0] txfifo_cnt;
|
wire [TX_FIFO_CNT_WIDTH-1:0] txfifo_cnt;
|
| Line 1024... |
Line 1023... |
// Enabling master wishbone access to the memory for two devices TX and RX.
|
// Enabling master wishbone access to the memory for two devices TX and RX.
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
begin
|
begin
|
MasterWbTX <=#Tp 1'b0;
|
MasterWbTX <= 1'b0;
|
MasterWbRX <=#Tp 1'b0;
|
MasterWbRX <= 1'b0;
|
m_wb_adr_o <=#Tp 30'h0;
|
m_wb_adr_o <= 30'h0;
|
m_wb_cyc_o <=#Tp 1'b0;
|
m_wb_cyc_o <= 1'b0;
|
m_wb_we_o <=#Tp 1'b0;
|
m_wb_we_o <= 1'b0;
|
m_wb_sel_o <=#Tp 4'h0;
|
m_wb_sel_o <= 4'h0;
|
cyc_cleared<=#Tp 1'b0;
|
cyc_cleared<= 1'b0;
|
tx_burst_cnt<=#Tp 0;
|
tx_burst_cnt<= 0;
|
rx_burst_cnt<=#Tp 0;
|
rx_burst_cnt<= 0;
|
IncrTxPointer<=#Tp 1'b0;
|
IncrTxPointer<= 1'b0;
|
tx_burst_en<=#Tp 1'b1;
|
tx_burst_en<= 1'b1;
|
rx_burst_en<=#Tp 1'b0;
|
rx_burst_en<= 1'b0;
|
`ifdef ETH_WISHBONE_B3
|
`ifdef ETH_WISHBONE_B3
|
m_wb_cti_o <=#Tp 3'b0;
|
m_wb_cti_o <= 3'b0;
|
`endif
|
`endif
|
end
|
end
|
else
|
else
|
begin
|
begin
|
// Switching between two stages depends on enable signals
|
// Switching between two stages depends on enable signals
|
| Line 1049... |
Line 1048... |
8'b00_10_00_10, // Idle and MRB needed
|
8'b00_10_00_10, // Idle and MRB needed
|
8'b10_1x_10_1x, // MRB continues
|
8'b10_1x_10_1x, // MRB continues
|
8'b10_10_01_10, // Clear (previously MR) and MRB needed
|
8'b10_10_01_10, // Clear (previously MR) and MRB needed
|
8'b01_1x_01_1x : // Clear (previously MW) and MRB needed
|
8'b01_1x_01_1x : // Clear (previously MW) and MRB needed
|
begin
|
begin
|
MasterWbTX <=#Tp 1'b1; // tx burst
|
MasterWbTX <= 1'b1; // tx burst
|
MasterWbRX <=#Tp 1'b0;
|
MasterWbRX <= 1'b0;
|
m_wb_cyc_o <=#Tp 1'b1;
|
m_wb_cyc_o <= 1'b1;
|
m_wb_we_o <=#Tp 1'b0;
|
m_wb_we_o <= 1'b0;
|
m_wb_sel_o <=#Tp 4'hf;
|
m_wb_sel_o <= 4'hf;
|
cyc_cleared<=#Tp 1'b0;
|
cyc_cleared<= 1'b0;
|
IncrTxPointer<=#Tp 1'b1;
|
IncrTxPointer<= 1'b1;
|
tx_burst_cnt <=#Tp tx_burst_cnt+3'h1;
|
tx_burst_cnt <= tx_burst_cnt+3'h1;
|
if(tx_burst_cnt==0)
|
if(tx_burst_cnt==0)
|
m_wb_adr_o <=#Tp TxPointerMSB;
|
m_wb_adr_o <= TxPointerMSB;
|
else
|
else
|
m_wb_adr_o <=#Tp m_wb_adr_o+1'b1;
|
m_wb_adr_o <= m_wb_adr_o+1'b1;
|
|
|
if(tx_burst_cnt==(`ETH_BURST_LENGTH-1))
|
if(tx_burst_cnt==(`ETH_BURST_LENGTH-1))
|
begin
|
begin
|
tx_burst_en<=#Tp 1'b0;
|
tx_burst_en<= 1'b0;
|
`ifdef ETH_WISHBONE_B3
|
`ifdef ETH_WISHBONE_B3
|
m_wb_cti_o <=#Tp 3'b111;
|
m_wb_cti_o <= 3'b111;
|
`endif
|
`endif
|
end
|
end
|
else
|
else
|
begin
|
begin
|
`ifdef ETH_WISHBONE_B3
|
`ifdef ETH_WISHBONE_B3
|
m_wb_cti_o <=#Tp 3'b010;
|
m_wb_cti_o <= 3'b010;
|
`endif
|
`endif
|
end
|
end
|
end
|
end
|
8'b00_x1_00_x1, // Idle and MWB needed
|
8'b00_x1_00_x1, // Idle and MWB needed
|
8'b01_x1_10_x1, // MWB continues
|
8'b01_x1_10_x1, // MWB continues
|
8'b01_01_01_01, // Clear (previously MW) and MWB needed
|
8'b01_01_01_01, // Clear (previously MW) and MWB needed
|
8'b10_x1_01_x1 : // Clear (previously MR) and MWB needed
|
8'b10_x1_01_x1 : // Clear (previously MR) and MWB needed
|
begin
|
begin
|
MasterWbTX <=#Tp 1'b0; // rx burst
|
MasterWbTX <= 1'b0; // rx burst
|
MasterWbRX <=#Tp 1'b1;
|
MasterWbRX <= 1'b1;
|
m_wb_cyc_o <=#Tp 1'b1;
|
m_wb_cyc_o <= 1'b1;
|
m_wb_we_o <=#Tp 1'b1;
|
m_wb_we_o <= 1'b1;
|
m_wb_sel_o <=#Tp RxByteSel;
|
m_wb_sel_o <= RxByteSel;
|
IncrTxPointer<=#Tp 1'b0;
|
IncrTxPointer<= 1'b0;
|
cyc_cleared<=#Tp 1'b0;
|
cyc_cleared<= 1'b0;
|
rx_burst_cnt <=#Tp rx_burst_cnt+3'h1;
|
rx_burst_cnt <= rx_burst_cnt+3'h1;
|
|
|
if(rx_burst_cnt==0)
|
if(rx_burst_cnt==0)
|
m_wb_adr_o <=#Tp RxPointerMSB;
|
m_wb_adr_o <= RxPointerMSB;
|
else
|
else
|
m_wb_adr_o <=#Tp m_wb_adr_o+1'b1;
|
m_wb_adr_o <= m_wb_adr_o+1'b1;
|
|
|
if(rx_burst_cnt==(`ETH_BURST_LENGTH-1))
|
if(rx_burst_cnt==(`ETH_BURST_LENGTH-1))
|
begin
|
begin
|
rx_burst_en<=#Tp 1'b0;
|
rx_burst_en<= 1'b0;
|
`ifdef ETH_WISHBONE_B3
|
`ifdef ETH_WISHBONE_B3
|
m_wb_cti_o <=#Tp 3'b111;
|
m_wb_cti_o <= 3'b111;
|
`endif
|
`endif
|
end
|
end
|
else
|
else
|
begin
|
begin
|
`ifdef ETH_WISHBONE_B3
|
`ifdef ETH_WISHBONE_B3
|
m_wb_cti_o <=#Tp 3'b010;
|
m_wb_cti_o <= 3'b010;
|
`endif
|
`endif
|
end
|
end
|
end
|
end
|
8'b00_x1_00_x0 : // idle and MW is needed (data write to rx buffer)
|
8'b00_x1_00_x0 : // idle and MW is needed (data write to rx buffer)
|
begin
|
begin
|
MasterWbTX <=#Tp 1'b0;
|
MasterWbTX <= 1'b0;
|
MasterWbRX <=#Tp 1'b1;
|
MasterWbRX <= 1'b1;
|
m_wb_adr_o <=#Tp RxPointerMSB;
|
m_wb_adr_o <= RxPointerMSB;
|
m_wb_cyc_o <=#Tp 1'b1;
|
m_wb_cyc_o <= 1'b1;
|
m_wb_we_o <=#Tp 1'b1;
|
m_wb_we_o <= 1'b1;
|
m_wb_sel_o <=#Tp RxByteSel;
|
m_wb_sel_o <= RxByteSel;
|
IncrTxPointer<=#Tp 1'b0;
|
IncrTxPointer<= 1'b0;
|
end
|
end
|
8'b00_10_00_00 : // idle and MR is needed (data read from tx buffer)
|
8'b00_10_00_00 : // idle and MR is needed (data read from tx buffer)
|
begin
|
begin
|
MasterWbTX <=#Tp 1'b1;
|
MasterWbTX <= 1'b1;
|
MasterWbRX <=#Tp 1'b0;
|
MasterWbRX <= 1'b0;
|
m_wb_adr_o <=#Tp TxPointerMSB;
|
m_wb_adr_o <= TxPointerMSB;
|
m_wb_cyc_o <=#Tp 1'b1;
|
m_wb_cyc_o <= 1'b1;
|
m_wb_we_o <=#Tp 1'b0;
|
m_wb_we_o <= 1'b0;
|
m_wb_sel_o <=#Tp 4'hf;
|
m_wb_sel_o <= 4'hf;
|
IncrTxPointer<=#Tp 1'b1;
|
IncrTxPointer<= 1'b1;
|
end
|
end
|
8'b10_10_01_00, // MR and MR is needed (data read from tx buffer)
|
8'b10_10_01_00, // MR and MR is needed (data read from tx buffer)
|
8'b01_1x_01_0x : // MW and MR is needed (data read from tx buffer)
|
8'b01_1x_01_0x : // MW and MR is needed (data read from tx buffer)
|
begin
|
begin
|
MasterWbTX <=#Tp 1'b1;
|
MasterWbTX <= 1'b1;
|
MasterWbRX <=#Tp 1'b0;
|
MasterWbRX <= 1'b0;
|
m_wb_adr_o <=#Tp TxPointerMSB;
|
m_wb_adr_o <= TxPointerMSB;
|
m_wb_cyc_o <=#Tp 1'b1;
|
m_wb_cyc_o <= 1'b1;
|
m_wb_we_o <=#Tp 1'b0;
|
m_wb_we_o <= 1'b0;
|
m_wb_sel_o <=#Tp 4'hf;
|
m_wb_sel_o <= 4'hf;
|
cyc_cleared<=#Tp 1'b0;
|
cyc_cleared<= 1'b0;
|
IncrTxPointer<=#Tp 1'b1;
|
IncrTxPointer<= 1'b1;
|
end
|
end
|
8'b01_01_01_00, // MW and MW needed (data write to rx buffer)
|
8'b01_01_01_00, // MW and MW needed (data write to rx buffer)
|
8'b10_x1_01_x0 : // MR and MW is needed (data write to rx buffer)
|
8'b10_x1_01_x0 : // MR and MW is needed (data write to rx buffer)
|
begin
|
begin
|
MasterWbTX <=#Tp 1'b0;
|
MasterWbTX <= 1'b0;
|
MasterWbRX <=#Tp 1'b1;
|
MasterWbRX <= 1'b1;
|
m_wb_adr_o <=#Tp RxPointerMSB;
|
m_wb_adr_o <= RxPointerMSB;
|
m_wb_cyc_o <=#Tp 1'b1;
|
m_wb_cyc_o <= 1'b1;
|
m_wb_we_o <=#Tp 1'b1;
|
m_wb_we_o <= 1'b1;
|
m_wb_sel_o <=#Tp RxByteSel;
|
m_wb_sel_o <= RxByteSel;
|
cyc_cleared<=#Tp 1'b0;
|
cyc_cleared<= 1'b0;
|
IncrTxPointer<=#Tp 1'b0;
|
IncrTxPointer<= 1'b0;
|
end
|
end
|
8'b01_01_10_00, // MW and MW needed (cycle is cleared between previous and next access)
|
8'b01_01_10_00, // MW and MW needed (cycle is cleared between previous and next access)
|
8'b01_1x_10_x0, // MW and MW or MR or MRB needed (cycle is cleared between previous and next access)
|
8'b01_1x_10_x0, // MW and MW or MR or MRB needed (cycle is cleared between previous and next access)
|
8'b10_10_10_00, // MR and MR needed (cycle is cleared between previous and next access)
|
8'b10_10_10_00, // MR and MR needed (cycle is cleared between previous and next access)
|
8'b10_x1_10_0x : // MR and MR or MW or MWB (cycle is cleared between previous and next access)
|
8'b10_x1_10_0x : // MR and MR or MW or MWB (cycle is cleared between previous and next access)
|
begin
|
begin
|
m_wb_cyc_o <=#Tp 1'b0; // whatever and master read or write is needed. We need to clear m_wb_cyc_o before next access is started
|
m_wb_cyc_o <= 1'b0; // whatever and master read or write is needed. We need to clear m_wb_cyc_o before next access is started
|
cyc_cleared<=#Tp 1'b1;
|
cyc_cleared<= 1'b1;
|
IncrTxPointer<=#Tp 1'b0;
|
IncrTxPointer<= 1'b0;
|
tx_burst_cnt<=#Tp 0;
|
tx_burst_cnt<= 0;
|
tx_burst_en<=#Tp txfifo_cnt<(TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4));
|
tx_burst_en<= txfifo_cnt<(TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4));
|
rx_burst_cnt<=#Tp 0;
|
rx_burst_cnt<= 0;
|
rx_burst_en<=#Tp MasterWbRX ? enough_data_in_rxfifo_for_burst_plus1 : enough_data_in_rxfifo_for_burst; // Counter is not decremented, yet, so plus1 is used.
|
rx_burst_en<= MasterWbRX ? enough_data_in_rxfifo_for_burst_plus1 : enough_data_in_rxfifo_for_burst; // Counter is not decremented, yet, so plus1 is used.
|
`ifdef ETH_WISHBONE_B3
|
`ifdef ETH_WISHBONE_B3
|
m_wb_cti_o <=#Tp 3'b0;
|
m_wb_cti_o <= 3'b0;
|
`endif
|
`endif
|
end
|
end
|
8'bxx_00_10_00, // whatever and no master read or write is needed (ack or err comes finishing previous access)
|
8'bxx_00_10_00, // whatever and no master read or write is needed (ack or err comes finishing previous access)
|
8'bxx_00_01_00 : // Between cyc_cleared request was cleared
|
8'bxx_00_01_00 : // Between cyc_cleared request was cleared
|
begin
|
begin
|
MasterWbTX <=#Tp 1'b0;
|
MasterWbTX <= 1'b0;
|
MasterWbRX <=#Tp 1'b0;
|
MasterWbRX <= 1'b0;
|
m_wb_cyc_o <=#Tp 1'b0;
|
m_wb_cyc_o <= 1'b0;
|
cyc_cleared<=#Tp 1'b0;
|
cyc_cleared<= 1'b0;
|
IncrTxPointer<=#Tp 1'b0;
|
IncrTxPointer<= 1'b0;
|
rx_burst_cnt<=#Tp 0;
|
rx_burst_cnt<= 0;
|
rx_burst_en<=#Tp MasterWbRX ? enough_data_in_rxfifo_for_burst_plus1 : enough_data_in_rxfifo_for_burst; // Counter is not decremented, yet, so plus1 is used.
|
rx_burst_en<= MasterWbRX ? enough_data_in_rxfifo_for_burst_plus1 : enough_data_in_rxfifo_for_burst; // Counter is not decremented, yet, so plus1 is used.
|
`ifdef ETH_WISHBONE_B3
|
`ifdef ETH_WISHBONE_B3
|
m_wb_cti_o <=#Tp 3'b0;
|
m_wb_cti_o <= 3'b0;
|
`endif
|
`endif
|
end
|
end
|
8'b00_00_00_00: // whatever and no master read or write is needed (ack or err comes finishing previous access)
|
8'b00_00_00_00: // whatever and no master read or write is needed (ack or err comes finishing previous access)
|
begin
|
begin
|
tx_burst_cnt<=#Tp 0;
|
tx_burst_cnt<= 0;
|
tx_burst_en<=#Tp txfifo_cnt<(TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4));
|
tx_burst_en<= txfifo_cnt<(TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4));
|
end
|
end
|
default: // Don't touch
|
default: // Don't touch
|
begin
|
begin
|
MasterWbTX <=#Tp MasterWbTX;
|
MasterWbTX <= MasterWbTX;
|
MasterWbRX <=#Tp MasterWbRX;
|
MasterWbRX <= MasterWbRX;
|
m_wb_cyc_o <=#Tp m_wb_cyc_o;
|
m_wb_cyc_o <= m_wb_cyc_o;
|
m_wb_sel_o <=#Tp m_wb_sel_o;
|
m_wb_sel_o <= m_wb_sel_o;
|
IncrTxPointer<=#Tp IncrTxPointer;
|
IncrTxPointer<= IncrTxPointer;
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
|
|
| Line 1207... |
Line 1206... |
|
|
assign TxFifoClear = (TxAbortPacket | TxRetryPacket);
|
assign TxFifoClear = (TxAbortPacket | TxRetryPacket);
|
|
|
eth_fifo #(.DATA_WIDTH(TX_FIFO_DATA_WIDTH),
|
eth_fifo #(.DATA_WIDTH(TX_FIFO_DATA_WIDTH),
|
.DEPTH(TX_FIFO_DEPTH),
|
.DEPTH(TX_FIFO_DEPTH),
|
.CNT_WIDTH(TX_FIFO_CNT_WIDTH),
|
.CNT_WIDTH(TX_FIFO_CNT_WIDTH))
|
.Tp(Tp))
|
|
tx_fifo ( .data_in(m_wb_dat_i), .data_out(TxData_wb),
|
tx_fifo ( .data_in(m_wb_dat_i), .data_out(TxData_wb),
|
.clk(WB_CLK_I), .reset(Reset),
|
.clk(WB_CLK_I), .reset(Reset),
|
.write(MasterWbTX & m_wb_ack_i), .read(ReadTxDataFromFifo_wb & ~TxBufferEmpty),
|
.write(MasterWbTX & m_wb_ack_i), .read(ReadTxDataFromFifo_wb & ~TxBufferEmpty),
|
.clear(TxFifoClear), .full(TxBufferFull),
|
.clear(TxFifoClear), .full(TxBufferFull),
|
.almost_full(TxBufferAlmostFull), .almost_empty(TxBufferAlmostEmpty),
|
.almost_full(TxBufferAlmostFull), .almost_empty(TxBufferAlmostEmpty),
|
| Line 1230... |
Line 1228... |
|
|
// Start: Generation of the TxStartFrm_wb which is then synchronized to the MTxClk
|
// Start: Generation of the TxStartFrm_wb which is then synchronized to the MTxClk
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
TxStartFrm_wb <=#Tp 1'b0;
|
TxStartFrm_wb <= 1'b0;
|
else
|
else
|
if(TxBDReady & ~StartOccured & (TxBufferFull | TxLengthEq0))
|
if(TxBDReady & ~StartOccured & (TxBufferFull | TxLengthEq0))
|
TxStartFrm_wb <=#Tp 1'b1;
|
TxStartFrm_wb <= 1'b1;
|
else
|
else
|
if(TxStartFrm_syncb2)
|
if(TxStartFrm_syncb2)
|
TxStartFrm_wb <=#Tp 1'b0;
|
TxStartFrm_wb <= 1'b0;
|
end
|
end
|
|
|
// StartOccured: TxStartFrm_wb occurs only ones at the beginning. Then it's blocked.
|
// StartOccured: TxStartFrm_wb occurs only ones at the beginning. Then it's blocked.
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
StartOccured <=#Tp 1'b0;
|
StartOccured <= 1'b0;
|
else
|
else
|
if(TxStartFrm_wb)
|
if(TxStartFrm_wb)
|
StartOccured <=#Tp 1'b1;
|
StartOccured <= 1'b1;
|
else
|
else
|
if(ResetTxBDReady)
|
if(ResetTxBDReady)
|
StartOccured <=#Tp 1'b0;
|
StartOccured <= 1'b0;
|
end
|
end
|
|
|
// Synchronizing TxStartFrm_wb to MTxClk
|
// Synchronizing TxStartFrm_wb to MTxClk
|
always @ (posedge MTxClk or posedge Reset)
|
always @ (posedge MTxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
TxStartFrm_sync1 <=#Tp 1'b0;
|
TxStartFrm_sync1 <= 1'b0;
|
else
|
else
|
TxStartFrm_sync1 <=#Tp TxStartFrm_wb;
|
TxStartFrm_sync1 <= TxStartFrm_wb;
|
end
|
end
|
|
|
always @ (posedge MTxClk or posedge Reset)
|
always @ (posedge MTxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
TxStartFrm_sync2 <=#Tp 1'b0;
|
TxStartFrm_sync2 <= 1'b0;
|
else
|
else
|
TxStartFrm_sync2 <=#Tp TxStartFrm_sync1;
|
TxStartFrm_sync2 <= TxStartFrm_sync1;
|
end
|
end
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
TxStartFrm_syncb1 <=#Tp 1'b0;
|
TxStartFrm_syncb1 <= 1'b0;
|
else
|
else
|
TxStartFrm_syncb1 <=#Tp TxStartFrm_sync2;
|
TxStartFrm_syncb1 <= TxStartFrm_sync2;
|
end
|
end
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
TxStartFrm_syncb2 <=#Tp 1'b0;
|
TxStartFrm_syncb2 <= 1'b0;
|
else
|
else
|
TxStartFrm_syncb2 <=#Tp TxStartFrm_syncb1;
|
TxStartFrm_syncb2 <= TxStartFrm_syncb1;
|
end
|
end
|
|
|
always @ (posedge MTxClk or posedge Reset)
|
always @ (posedge MTxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
TxStartFrm <=#Tp 1'b0;
|
TxStartFrm <= 1'b0;
|
else
|
else
|
if(TxStartFrm_sync2)
|
if(TxStartFrm_sync2)
|
TxStartFrm <=#Tp 1'b1;
|
TxStartFrm <= 1'b1;
|
else
|
else
|
if(TxUsedData_q | ~TxStartFrm_sync2 & (TxRetry & (~TxRetry_q) | TxAbort & (~TxAbort_q)))
|
if(TxUsedData_q | ~TxStartFrm_sync2 & (TxRetry & (~TxRetry_q) | TxAbort & (~TxAbort_q)))
|
TxStartFrm <=#Tp 1'b0;
|
TxStartFrm <= 1'b0;
|
end
|
end
|
// End: Generation of the TxStartFrm_wb which is then synchronized to the MTxClk
|
// End: Generation of the TxStartFrm_wb which is then synchronized to the MTxClk
|
|
|
|
|
// TxEndFrm_wb: indicator of the end of frame
|
// TxEndFrm_wb: indicator of the end of frame
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
TxEndFrm_wb <=#Tp 1'b0;
|
TxEndFrm_wb <= 1'b0;
|
else
|
else
|
if(TxLengthEq0 & TxBufferAlmostEmpty & TxUsedData)
|
if(TxLengthEq0 & TxBufferAlmostEmpty & TxUsedData)
|
TxEndFrm_wb <=#Tp 1'b1;
|
TxEndFrm_wb <= 1'b1;
|
else
|
else
|
if(TxRetryPulse | TxDonePulse | TxAbortPulse)
|
if(TxRetryPulse | TxDonePulse | TxAbortPulse)
|
TxEndFrm_wb <=#Tp 1'b0;
|
TxEndFrm_wb <= 1'b0;
|
end
|
end
|
|
|
|
|
// Marks which bytes are valid within the word.
|
// Marks which bytes are valid within the word.
|
assign TxValidBytes = TxLengthLt4 ? TxLength[1:0] : 2'b0;
|
assign TxValidBytes = TxLengthLt4 ? TxLength[1:0] : 2'b0;
|
| Line 1322... |
Line 1320... |
reg LatchValidBytes_q;
|
reg LatchValidBytes_q;
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
LatchValidBytes <=#Tp 1'b0;
|
LatchValidBytes <= 1'b0;
|
else
|
else
|
if(TxLengthLt4 & TxBDReady)
|
if(TxLengthLt4 & TxBDReady)
|
LatchValidBytes <=#Tp 1'b1;
|
LatchValidBytes <= 1'b1;
|
else
|
else
|
LatchValidBytes <=#Tp 1'b0;
|
LatchValidBytes <= 1'b0;
|
end
|
end
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
LatchValidBytes_q <=#Tp 1'b0;
|
LatchValidBytes_q <= 1'b0;
|
else
|
else
|
LatchValidBytes_q <=#Tp LatchValidBytes;
|
LatchValidBytes_q <= LatchValidBytes;
|
end
|
end
|
|
|
|
|
// Latching valid bytes
|
// Latching valid bytes
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
TxValidBytesLatched <=#Tp 2'h0;
|
TxValidBytesLatched <= 2'h0;
|
else
|
else
|
if(LatchValidBytes & ~LatchValidBytes_q)
|
if(LatchValidBytes & ~LatchValidBytes_q)
|
TxValidBytesLatched <=#Tp TxValidBytes;
|
TxValidBytesLatched <= TxValidBytes;
|
else
|
else
|
if(TxRetryPulse | TxDonePulse | TxAbortPulse)
|
if(TxRetryPulse | TxDonePulse | TxAbortPulse)
|
TxValidBytesLatched <=#Tp 2'h0;
|
TxValidBytesLatched <= 2'h0;
|
end
|
end
|
|
|
|
|
assign TxIRQEn = TxStatus[14];
|
assign TxIRQEn = TxStatus[14];
|
assign WrapTxStatusBit = TxStatus[13];
|
assign WrapTxStatusBit = TxStatus[13];
|
| Line 1373... |
Line 1371... |
|
|
// Latching Tx buffer descriptor address
|
// Latching Tx buffer descriptor address
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
TxBDAddress <=#Tp 7'h0;
|
TxBDAddress <= 7'h0;
|
else if (r_TxEn & (~r_TxEn_q))
|
else if (r_TxEn & (~r_TxEn_q))
|
TxBDAddress <=#Tp 7'h0;
|
TxBDAddress <= 7'h0;
|
else if (TxStatusWrite)
|
else if (TxStatusWrite)
|
TxBDAddress <=#Tp TempTxBDAddress;
|
TxBDAddress <= TempTxBDAddress;
|
end
|
end
|
|
|
|
|
// Latching Rx buffer descriptor address
|
// Latching Rx buffer descriptor address
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
RxBDAddress <=#Tp 7'h0;
|
RxBDAddress <= 7'h0;
|
else if(r_RxEn & (~r_RxEn_q))
|
else if(r_RxEn & (~r_RxEn_q))
|
RxBDAddress <=#Tp r_TxBDNum[6:0];
|
RxBDAddress <= r_TxBDNum[6:0];
|
else if(RxStatusWrite)
|
else if(RxStatusWrite)
|
RxBDAddress <=#Tp TempRxBDAddress;
|
RxBDAddress <= TempRxBDAddress;
|
end
|
end
|
|
|
wire [8:0] TxStatusInLatched = {TxUnderRun, RetryCntLatched[3:0], RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost};
|
wire [8:0] TxStatusInLatched = {TxUnderRun, RetryCntLatched[3:0], RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost};
|
|
|
assign RxBDDataIn = {LatchedRxLength, 1'b0, RxStatus, 4'h0, RxStatusInLatched};
|
assign RxBDDataIn = {LatchedRxLength, 1'b0, RxStatus, 4'h0, RxStatusInLatched};
|
| Line 1410... |
Line 1408... |
// Generating delayed signals
|
// Generating delayed signals
|
always @ (posedge MTxClk or posedge Reset)
|
always @ (posedge MTxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
begin
|
begin
|
TxAbort_q <=#Tp 1'b0;
|
TxAbort_q <= 1'b0;
|
TxRetry_q <=#Tp 1'b0;
|
TxRetry_q <= 1'b0;
|
TxUsedData_q <=#Tp 1'b0;
|
TxUsedData_q <= 1'b0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
TxAbort_q <=#Tp TxAbort;
|
TxAbort_q <= TxAbort;
|
TxRetry_q <=#Tp TxRetry;
|
TxRetry_q <= TxRetry;
|
TxUsedData_q <=#Tp TxUsedData;
|
TxUsedData_q <= TxUsedData;
|
end
|
end
|
end
|
end
|
|
|
// Generating delayed signals
|
// Generating delayed signals
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
begin
|
begin
|
TxDone_wb_q <=#Tp 1'b0;
|
TxDone_wb_q <= 1'b0;
|
TxAbort_wb_q <=#Tp 1'b0;
|
TxAbort_wb_q <= 1'b0;
|
TxRetry_wb_q <=#Tp 1'b0;
|
TxRetry_wb_q <= 1'b0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
TxDone_wb_q <=#Tp TxDone_wb;
|
TxDone_wb_q <= TxDone_wb;
|
TxAbort_wb_q <=#Tp TxAbort_wb;
|
TxAbort_wb_q <= TxAbort_wb;
|
TxRetry_wb_q <=#Tp TxRetry_wb;
|
TxRetry_wb_q <= TxRetry_wb;
|
end
|
end
|
end
|
end
|
|
|
|
|
reg TxAbortPacketBlocked;
|
reg TxAbortPacketBlocked;
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
TxAbortPacket <=#Tp 1'b0;
|
TxAbortPacket <= 1'b0;
|
else
|
else
|
if(TxAbort_wb & (~tx_burst_en) & MasterWbTX & MasterAccessFinished & (~TxAbortPacketBlocked) |
|
if(TxAbort_wb & (~tx_burst_en) & MasterWbTX & MasterAccessFinished & (~TxAbortPacketBlocked) |
|
TxAbort_wb & (~MasterWbTX) & (~TxAbortPacketBlocked))
|
TxAbort_wb & (~MasterWbTX) & (~TxAbortPacketBlocked))
|
TxAbortPacket <=#Tp 1'b1;
|
TxAbortPacket <= 1'b1;
|
else
|
else
|
TxAbortPacket <=#Tp 1'b0;
|
TxAbortPacket <= 1'b0;
|
end
|
end
|
|
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
TxAbortPacket_NotCleared <=#Tp 1'b0;
|
TxAbortPacket_NotCleared <= 1'b0;
|
else
|
else
|
if(TxEn & TxEn_q & TxAbortPacket_NotCleared)
|
if(TxEn & TxEn_q & TxAbortPacket_NotCleared)
|
TxAbortPacket_NotCleared <=#Tp 1'b0;
|
TxAbortPacket_NotCleared <= 1'b0;
|
else
|
else
|
if(TxAbort_wb & (~tx_burst_en) & MasterWbTX & MasterAccessFinished & (~TxAbortPacketBlocked) |
|
if(TxAbort_wb & (~tx_burst_en) & MasterWbTX & MasterAccessFinished & (~TxAbortPacketBlocked) |
|
TxAbort_wb & (~MasterWbTX) & (~TxAbortPacketBlocked))
|
TxAbort_wb & (~MasterWbTX) & (~TxAbortPacketBlocked))
|
TxAbortPacket_NotCleared <=#Tp 1'b1;
|
TxAbortPacket_NotCleared <= 1'b1;
|
end
|
end
|
|
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
TxAbortPacketBlocked <=#Tp 1'b0;
|
TxAbortPacketBlocked <= 1'b0;
|
else
|
else
|
if(!TxAbort_wb & TxAbort_wb_q)
|
if(!TxAbort_wb & TxAbort_wb_q)
|
TxAbortPacketBlocked <=#Tp 1'b0;
|
TxAbortPacketBlocked <= 1'b0;
|
else
|
else
|
if(TxAbortPacket)
|
if(TxAbortPacket)
|
TxAbortPacketBlocked <=#Tp 1'b1;
|
TxAbortPacketBlocked <= 1'b1;
|
end
|
end
|
|
|
|
|
reg TxRetryPacketBlocked;
|
reg TxRetryPacketBlocked;
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
TxRetryPacket <=#Tp 1'b0;
|
TxRetryPacket <= 1'b0;
|
else
|
else
|
if(TxRetry_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & !TxRetryPacketBlocked |
|
if(TxRetry_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & !TxRetryPacketBlocked |
|
TxRetry_wb & !MasterWbTX & !TxRetryPacketBlocked)
|
TxRetry_wb & !MasterWbTX & !TxRetryPacketBlocked)
|
TxRetryPacket <=#Tp 1'b1;
|
TxRetryPacket <= 1'b1;
|
else
|
else
|
TxRetryPacket <=#Tp 1'b0;
|
TxRetryPacket <= 1'b0;
|
end
|
end
|
|
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
TxRetryPacket_NotCleared <=#Tp 1'b0;
|
TxRetryPacket_NotCleared <= 1'b0;
|
else
|
else
|
if(StartTxBDRead)
|
if(StartTxBDRead)
|
TxRetryPacket_NotCleared <=#Tp 1'b0;
|
TxRetryPacket_NotCleared <= 1'b0;
|
else
|
else
|
if(TxRetry_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & !TxRetryPacketBlocked |
|
if(TxRetry_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & !TxRetryPacketBlocked |
|
TxRetry_wb & !MasterWbTX & !TxRetryPacketBlocked)
|
TxRetry_wb & !MasterWbTX & !TxRetryPacketBlocked)
|
TxRetryPacket_NotCleared <=#Tp 1'b1;
|
TxRetryPacket_NotCleared <= 1'b1;
|
end
|
end
|
|
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
TxRetryPacketBlocked <=#Tp 1'b0;
|
TxRetryPacketBlocked <= 1'b0;
|
else
|
else
|
if(!TxRetry_wb & TxRetry_wb_q)
|
if(!TxRetry_wb & TxRetry_wb_q)
|
TxRetryPacketBlocked <=#Tp 1'b0;
|
TxRetryPacketBlocked <= 1'b0;
|
else
|
else
|
if(TxRetryPacket)
|
if(TxRetryPacket)
|
TxRetryPacketBlocked <=#Tp 1'b1;
|
TxRetryPacketBlocked <= 1'b1;
|
end
|
end
|
|
|
|
|
reg TxDonePacketBlocked;
|
reg TxDonePacketBlocked;
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
TxDonePacket <=#Tp 1'b0;
|
TxDonePacket <= 1'b0;
|
else
|
else
|
if(TxDone_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & !TxDonePacketBlocked |
|
if(TxDone_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & !TxDonePacketBlocked |
|
TxDone_wb & !MasterWbTX & !TxDonePacketBlocked)
|
TxDone_wb & !MasterWbTX & !TxDonePacketBlocked)
|
TxDonePacket <=#Tp 1'b1;
|
TxDonePacket <= 1'b1;
|
else
|
else
|
TxDonePacket <=#Tp 1'b0;
|
TxDonePacket <= 1'b0;
|
end
|
end
|
|
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
TxDonePacket_NotCleared <=#Tp 1'b0;
|
TxDonePacket_NotCleared <= 1'b0;
|
else
|
else
|
if(TxEn & TxEn_q & TxDonePacket_NotCleared)
|
if(TxEn & TxEn_q & TxDonePacket_NotCleared)
|
TxDonePacket_NotCleared <=#Tp 1'b0;
|
TxDonePacket_NotCleared <= 1'b0;
|
else
|
else
|
if(TxDone_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & (~TxDonePacketBlocked) |
|
if(TxDone_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & (~TxDonePacketBlocked) |
|
TxDone_wb & !MasterWbTX & (~TxDonePacketBlocked))
|
TxDone_wb & !MasterWbTX & (~TxDonePacketBlocked))
|
TxDonePacket_NotCleared <=#Tp 1'b1;
|
TxDonePacket_NotCleared <= 1'b1;
|
end
|
end
|
|
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
TxDonePacketBlocked <=#Tp 1'b0;
|
TxDonePacketBlocked <= 1'b0;
|
else
|
else
|
if(!TxDone_wb & TxDone_wb_q)
|
if(!TxDone_wb & TxDone_wb_q)
|
TxDonePacketBlocked <=#Tp 1'b0;
|
TxDonePacketBlocked <= 1'b0;
|
else
|
else
|
if(TxDonePacket)
|
if(TxDonePacket)
|
TxDonePacketBlocked <=#Tp 1'b1;
|
TxDonePacketBlocked <= 1'b1;
|
end
|
end
|
|
|
|
|
// Indication of the last word
|
// Indication of the last word
|
always @ (posedge MTxClk or posedge Reset)
|
always @ (posedge MTxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
LastWord <=#Tp 1'b0;
|
LastWord <= 1'b0;
|
else
|
else
|
if((TxEndFrm | TxAbort | TxRetry) & Flop)
|
if((TxEndFrm | TxAbort | TxRetry) & Flop)
|
LastWord <=#Tp 1'b0;
|
LastWord <= 1'b0;
|
else
|
else
|
if(TxUsedData & Flop & TxByteCnt == 2'h3)
|
if(TxUsedData & Flop & TxByteCnt == 2'h3)
|
LastWord <=#Tp TxEndFrm_wb;
|
LastWord <= TxEndFrm_wb;
|
end
|
end
|
|
|
|
|
// Tx end frame generation
|
// Tx end frame generation
|
always @ (posedge MTxClk or posedge Reset)
|
always @ (posedge MTxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
TxEndFrm <=#Tp 1'b0;
|
TxEndFrm <= 1'b0;
|
else
|
else
|
if(Flop & TxEndFrm | TxAbort | TxRetry_q)
|
if(Flop & TxEndFrm | TxAbort | TxRetry_q)
|
TxEndFrm <=#Tp 1'b0;
|
TxEndFrm <= 1'b0;
|
else
|
else
|
if(Flop & LastWord)
|
if(Flop & LastWord)
|
begin
|
begin
|
case (TxValidBytesLatched) // synopsys parallel_case
|
case (TxValidBytesLatched) // synopsys parallel_case
|
1 : TxEndFrm <=#Tp TxByteCnt == 2'h0;
|
1 : TxEndFrm <= TxByteCnt == 2'h0;
|
2 : TxEndFrm <=#Tp TxByteCnt == 2'h1;
|
2 : TxEndFrm <= TxByteCnt == 2'h1;
|
3 : TxEndFrm <=#Tp TxByteCnt == 2'h2;
|
3 : TxEndFrm <= TxByteCnt == 2'h2;
|
0 : TxEndFrm <=#Tp TxByteCnt == 2'h3;
|
0 : TxEndFrm <= TxByteCnt == 2'h3;
|
default : TxEndFrm <=#Tp 1'b0;
|
default : TxEndFrm <= 1'b0;
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
|
|
|
|
// Tx data selection (latching)
|
// Tx data selection (latching)
|
always @ (posedge MTxClk or posedge Reset)
|
always @ (posedge MTxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
TxData <=#Tp 0;
|
TxData <= 0;
|
else
|
else
|
if(TxStartFrm_sync2 & ~TxStartFrm)
|
if(TxStartFrm_sync2 & ~TxStartFrm)
|
case(TxPointerLSB) // synopsys parallel_case
|
case(TxPointerLSB) // synopsys parallel_case
|
2'h0 : TxData <=#Tp TxData_wb[31:24]; // Big Endian Byte Ordering
|
2'h0 : TxData <= TxData_wb[31:24]; // Big Endian Byte Ordering
|
2'h1 : TxData <=#Tp TxData_wb[23:16]; // Big Endian Byte Ordering
|
2'h1 : TxData <= TxData_wb[23:16]; // Big Endian Byte Ordering
|
2'h2 : TxData <=#Tp TxData_wb[15:08]; // Big Endian Byte Ordering
|
2'h2 : TxData <= TxData_wb[15:08]; // Big Endian Byte Ordering
|
2'h3 : TxData <=#Tp TxData_wb[07:00]; // Big Endian Byte Ordering
|
2'h3 : TxData <= TxData_wb[07:00]; // Big Endian Byte Ordering
|
endcase
|
endcase
|
else
|
else
|
if(TxStartFrm & TxUsedData & TxPointerLSB==2'h3)
|
if(TxStartFrm & TxUsedData & TxPointerLSB==2'h3)
|
TxData <=#Tp TxData_wb[31:24]; // Big Endian Byte Ordering
|
TxData <= TxData_wb[31:24]; // Big Endian Byte Ordering
|
else
|
else
|
if(TxUsedData & Flop)
|
if(TxUsedData & Flop)
|
begin
|
begin
|
case(TxByteCnt) // synopsys parallel_case
|
case(TxByteCnt) // synopsys parallel_case
|
0 : TxData <=#Tp TxDataLatched[31:24]; // Big Endian Byte Ordering
|
0 : TxData <= TxDataLatched[31:24]; // Big Endian Byte Ordering
|
1 : TxData <=#Tp TxDataLatched[23:16];
|
1 : TxData <= TxDataLatched[23:16];
|
2 : TxData <=#Tp TxDataLatched[15:8];
|
2 : TxData <= TxDataLatched[15:8];
|
3 : TxData <=#Tp TxDataLatched[7:0];
|
3 : TxData <= TxDataLatched[7:0];
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
|
|
|
|
// Latching tx data
|
// Latching tx data
|
always @ (posedge MTxClk or posedge Reset)
|
always @ (posedge MTxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
TxDataLatched[31:0] <=#Tp 32'h0;
|
TxDataLatched[31:0] <= 32'h0;
|
else
|
else
|
if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop & TxByteCnt == 2'h3 | TxStartFrm & TxUsedData & Flop & TxByteCnt == 2'h0)
|
if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop & TxByteCnt == 2'h3 | TxStartFrm & TxUsedData & Flop & TxByteCnt == 2'h0)
|
TxDataLatched[31:0] <=#Tp TxData_wb[31:0];
|
TxDataLatched[31:0] <= TxData_wb[31:0];
|
end
|
end
|
|
|
|
|
// Tx under run
|
// Tx under run
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
TxUnderRun_wb <=#Tp 1'b0;
|
TxUnderRun_wb <= 1'b0;
|
else
|
else
|
if(TxAbortPulse)
|
if(TxAbortPulse)
|
TxUnderRun_wb <=#Tp 1'b0;
|
TxUnderRun_wb <= 1'b0;
|
else
|
else
|
if(TxBufferEmpty & ReadTxDataFromFifo_wb)
|
if(TxBufferEmpty & ReadTxDataFromFifo_wb)
|
TxUnderRun_wb <=#Tp 1'b1;
|
TxUnderRun_wb <= 1'b1;
|
end
|
end
|
|
|
|
|
reg TxUnderRun_sync1;
|
reg TxUnderRun_sync1;
|
|
|
// Tx under run
|
// Tx under run
|
always @ (posedge MTxClk or posedge Reset)
|
always @ (posedge MTxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
TxUnderRun_sync1 <=#Tp 1'b0;
|
TxUnderRun_sync1 <= 1'b0;
|
else
|
else
|
if(TxUnderRun_wb)
|
if(TxUnderRun_wb)
|
TxUnderRun_sync1 <=#Tp 1'b1;
|
TxUnderRun_sync1 <= 1'b1;
|
else
|
else
|
if(BlockingTxStatusWrite_sync2)
|
if(BlockingTxStatusWrite_sync2)
|
TxUnderRun_sync1 <=#Tp 1'b0;
|
TxUnderRun_sync1 <= 1'b0;
|
end
|
end
|
|
|
// Tx under run
|
// Tx under run
|
always @ (posedge MTxClk or posedge Reset)
|
always @ (posedge MTxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
TxUnderRun <=#Tp 1'b0;
|
TxUnderRun <= 1'b0;
|
else
|
else
|
if(BlockingTxStatusWrite_sync2)
|
if(BlockingTxStatusWrite_sync2)
|
TxUnderRun <=#Tp 1'b0;
|
TxUnderRun <= 1'b0;
|
else
|
else
|
if(TxUnderRun_sync1)
|
if(TxUnderRun_sync1)
|
TxUnderRun <=#Tp 1'b1;
|
TxUnderRun <= 1'b1;
|
end
|
end
|
|
|
|
|
// Tx Byte counter
|
// Tx Byte counter
|
always @ (posedge MTxClk or posedge Reset)
|
always @ (posedge MTxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
TxByteCnt <=#Tp 2'h0;
|
TxByteCnt <= 2'h0;
|
else
|
else
|
if(TxAbort_q | TxRetry_q)
|
if(TxAbort_q | TxRetry_q)
|
TxByteCnt <=#Tp 2'h0;
|
TxByteCnt <= 2'h0;
|
else
|
else
|
if(TxStartFrm & ~TxUsedData)
|
if(TxStartFrm & ~TxUsedData)
|
case(TxPointerLSB) // synopsys parallel_case
|
case(TxPointerLSB) // synopsys parallel_case
|
2'h0 : TxByteCnt <=#Tp 2'h1;
|
2'h0 : TxByteCnt <= 2'h1;
|
2'h1 : TxByteCnt <=#Tp 2'h2;
|
2'h1 : TxByteCnt <= 2'h2;
|
2'h2 : TxByteCnt <=#Tp 2'h3;
|
2'h2 : TxByteCnt <= 2'h3;
|
2'h3 : TxByteCnt <=#Tp 2'h0;
|
2'h3 : TxByteCnt <= 2'h0;
|
endcase
|
endcase
|
else
|
else
|
if(TxUsedData & Flop)
|
if(TxUsedData & Flop)
|
TxByteCnt <=#Tp TxByteCnt + 1'b1;
|
TxByteCnt <= TxByteCnt + 1'b1;
|
end
|
end
|
|
|
|
|
// Start: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I
|
// Start: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I
|
reg ReadTxDataFromFifo_sync1;
|
reg ReadTxDataFromFifo_sync1;
|
| Line 1716... |
Line 1714... |
|
|
|
|
always @ (posedge MTxClk or posedge Reset)
|
always @ (posedge MTxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
ReadTxDataFromFifo_tck <=#Tp 1'b0;
|
ReadTxDataFromFifo_tck <= 1'b0;
|
else
|
else
|
if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop & TxByteCnt == 2'h3 & ~LastWord | TxStartFrm & TxUsedData & Flop & TxByteCnt == 2'h0)
|
if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop & TxByteCnt == 2'h3 & ~LastWord | TxStartFrm & TxUsedData & Flop & TxByteCnt == 2'h0)
|
ReadTxDataFromFifo_tck <=#Tp 1'b1;
|
ReadTxDataFromFifo_tck <= 1'b1;
|
else
|
else
|
if(ReadTxDataFromFifo_syncb2 & ~ReadTxDataFromFifo_syncb3)
|
if(ReadTxDataFromFifo_syncb2 & ~ReadTxDataFromFifo_syncb3)
|
ReadTxDataFromFifo_tck <=#Tp 1'b0;
|
ReadTxDataFromFifo_tck <= 1'b0;
|
end
|
end
|
|
|
// Synchronizing TxStartFrm_wb to MTxClk
|
// Synchronizing TxStartFrm_wb to MTxClk
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
ReadTxDataFromFifo_sync1 <=#Tp 1'b0;
|
ReadTxDataFromFifo_sync1 <= 1'b0;
|
else
|
else
|
ReadTxDataFromFifo_sync1 <=#Tp ReadTxDataFromFifo_tck;
|
ReadTxDataFromFifo_sync1 <= ReadTxDataFromFifo_tck;
|
end
|
end
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
ReadTxDataFromFifo_sync2 <=#Tp 1'b0;
|
ReadTxDataFromFifo_sync2 <= 1'b0;
|
else
|
else
|
ReadTxDataFromFifo_sync2 <=#Tp ReadTxDataFromFifo_sync1;
|
ReadTxDataFromFifo_sync2 <= ReadTxDataFromFifo_sync1;
|
end
|
end
|
|
|
always @ (posedge MTxClk or posedge Reset)
|
always @ (posedge MTxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
ReadTxDataFromFifo_syncb1 <=#Tp 1'b0;
|
ReadTxDataFromFifo_syncb1 <= 1'b0;
|
else
|
else
|
ReadTxDataFromFifo_syncb1 <=#Tp ReadTxDataFromFifo_sync2;
|
ReadTxDataFromFifo_syncb1 <= ReadTxDataFromFifo_sync2;
|
end
|
end
|
|
|
always @ (posedge MTxClk or posedge Reset)
|
always @ (posedge MTxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
ReadTxDataFromFifo_syncb2 <=#Tp 1'b0;
|
ReadTxDataFromFifo_syncb2 <= 1'b0;
|
else
|
else
|
ReadTxDataFromFifo_syncb2 <=#Tp ReadTxDataFromFifo_syncb1;
|
ReadTxDataFromFifo_syncb2 <= ReadTxDataFromFifo_syncb1;
|
end
|
end
|
|
|
always @ (posedge MTxClk or posedge Reset)
|
always @ (posedge MTxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
ReadTxDataFromFifo_syncb3 <=#Tp 1'b0;
|
ReadTxDataFromFifo_syncb3 <= 1'b0;
|
else
|
else
|
ReadTxDataFromFifo_syncb3 <=#Tp ReadTxDataFromFifo_syncb2;
|
ReadTxDataFromFifo_syncb3 <= ReadTxDataFromFifo_syncb2;
|
end
|
end
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
ReadTxDataFromFifo_sync3 <=#Tp 1'b0;
|
ReadTxDataFromFifo_sync3 <= 1'b0;
|
else
|
else
|
ReadTxDataFromFifo_sync3 <=#Tp ReadTxDataFromFifo_sync2;
|
ReadTxDataFromFifo_sync3 <= ReadTxDataFromFifo_sync2;
|
end
|
end
|
|
|
assign ReadTxDataFromFifo_wb = ReadTxDataFromFifo_sync2 & ~ReadTxDataFromFifo_sync3;
|
assign ReadTxDataFromFifo_wb = ReadTxDataFromFifo_sync2 & ~ReadTxDataFromFifo_sync3;
|
// End: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I
|
// End: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I
|
|
|
|
|
// Synchronizing TxRetry signal (synchronized to WISHBONE clock)
|
// Synchronizing TxRetry signal (synchronized to WISHBONE clock)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
TxRetrySync1 <=#Tp 1'b0;
|
TxRetrySync1 <= 1'b0;
|
else
|
else
|
TxRetrySync1 <=#Tp TxRetry;
|
TxRetrySync1 <= TxRetry;
|
end
|
end
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
TxRetry_wb <=#Tp 1'b0;
|
TxRetry_wb <= 1'b0;
|
else
|
else
|
TxRetry_wb <=#Tp TxRetrySync1;
|
TxRetry_wb <= TxRetrySync1;
|
end
|
end
|
|
|
|
|
// Synchronized TxDone_wb signal (synchronized to WISHBONE clock)
|
// Synchronized TxDone_wb signal (synchronized to WISHBONE clock)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
TxDoneSync1 <=#Tp 1'b0;
|
TxDoneSync1 <= 1'b0;
|
else
|
else
|
TxDoneSync1 <=#Tp TxDone;
|
TxDoneSync1 <= TxDone;
|
end
|
end
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
TxDone_wb <=#Tp 1'b0;
|
TxDone_wb <= 1'b0;
|
else
|
else
|
TxDone_wb <=#Tp TxDoneSync1;
|
TxDone_wb <= TxDoneSync1;
|
end
|
end
|
|
|
// Synchronizing TxAbort signal (synchronized to WISHBONE clock)
|
// Synchronizing TxAbort signal (synchronized to WISHBONE clock)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
TxAbortSync1 <=#Tp 1'b0;
|
TxAbortSync1 <= 1'b0;
|
else
|
else
|
TxAbortSync1 <=#Tp TxAbort;
|
TxAbortSync1 <= TxAbort;
|
end
|
end
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
TxAbort_wb <=#Tp 1'b0;
|
TxAbort_wb <= 1'b0;
|
else
|
else
|
TxAbort_wb <=#Tp TxAbortSync1;
|
TxAbort_wb <= TxAbortSync1;
|
end
|
end
|
|
|
|
|
reg RxAbortSync1;
|
reg RxAbortSync1;
|
reg RxAbortSync2;
|
reg RxAbortSync2;
|
| Line 1844... |
Line 1842... |
|
|
// Reading the Rx buffer descriptor
|
// Reading the Rx buffer descriptor
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
RxBDRead <=#Tp 1'b0;
|
RxBDRead <= 1'b0;
|
else
|
else
|
if(StartRxBDRead & ~RxReady)
|
if(StartRxBDRead & ~RxReady)
|
RxBDRead <=#Tp 1'b1;
|
RxBDRead <= 1'b1;
|
else
|
else
|
if(RxBDReady)
|
if(RxBDReady)
|
RxBDRead <=#Tp 1'b0;
|
RxBDRead <= 1'b0;
|
end
|
end
|
|
|
|
|
// Reading of the next receive buffer descriptor starts after reception status is
|
// Reading of the next receive buffer descriptor starts after reception status is
|
// written to the previous one.
|
// written to the previous one.
|
|
|
// Latching READY status of the Rx buffer descriptor
|
// Latching READY status of the Rx buffer descriptor
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
RxBDReady <=#Tp 1'b0;
|
RxBDReady <= 1'b0;
|
else
|
else
|
if(RxPointerRead)
|
if(RxPointerRead)
|
RxBDReady <=#Tp 1'b0;
|
RxBDReady <= 1'b0;
|
else
|
else
|
if(RxEn & RxEn_q & RxBDRead)
|
if(RxEn & RxEn_q & RxBDRead)
|
RxBDReady <=#Tp ram_do[15]; // RxBDReady is sampled only once at the beginning
|
RxBDReady <= ram_do[15]; // RxBDReady is sampled only once at the beginning
|
end
|
end
|
|
|
// Latching Rx buffer descriptor status
|
// Latching Rx buffer descriptor status
|
// Data is avaliable one cycle after the access is started (at that time signal RxEn is not active)
|
// Data is avaliable one cycle after the access is started (at that time signal RxEn is not active)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
RxStatus <=#Tp 2'h0;
|
RxStatus <= 2'h0;
|
else
|
else
|
if(RxEn & RxEn_q & RxBDRead)
|
if(RxEn & RxEn_q & RxBDRead)
|
RxStatus <=#Tp ram_do[14:13];
|
RxStatus <= ram_do[14:13];
|
end
|
end
|
|
|
|
|
// RxReady generation
|
// RxReady generation
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
RxReady <=#Tp 1'b0;
|
RxReady <= 1'b0;
|
else
|
else
|
if(ShiftEnded | RxAbortSync2 & ~RxAbortSync3 | ~r_RxEn & r_RxEn_q)
|
if(ShiftEnded | RxAbortSync2 & ~RxAbortSync3 | ~r_RxEn & r_RxEn_q)
|
RxReady <=#Tp 1'b0;
|
RxReady <= 1'b0;
|
else
|
else
|
if(RxEn & RxEn_q & RxPointerRead)
|
if(RxEn & RxEn_q & RxPointerRead)
|
RxReady <=#Tp 1'b1;
|
RxReady <= 1'b1;
|
end
|
end
|
|
|
|
|
// Reading Rx BD pointer
|
// Reading Rx BD pointer
|
|
|
| Line 1905... |
Line 1903... |
|
|
// Reading Tx BD Pointer
|
// Reading Tx BD Pointer
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
RxPointerRead <=#Tp 1'b0;
|
RxPointerRead <= 1'b0;
|
else
|
else
|
if(StartRxPointerRead)
|
if(StartRxPointerRead)
|
RxPointerRead <=#Tp 1'b1;
|
RxPointerRead <= 1'b1;
|
else
|
else
|
if(RxEn & RxEn_q)
|
if(RxEn & RxEn_q)
|
RxPointerRead <=#Tp 1'b0;
|
RxPointerRead <= 1'b0;
|
end
|
end
|
|
|
|
|
//Latching Rx buffer pointer from buffer descriptor;
|
//Latching Rx buffer pointer from buffer descriptor;
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
RxPointerMSB <=#Tp 30'h0;
|
RxPointerMSB <= 30'h0;
|
else
|
else
|
if(RxEn & RxEn_q & RxPointerRead)
|
if(RxEn & RxEn_q & RxPointerRead)
|
RxPointerMSB <=#Tp ram_do[31:2];
|
RxPointerMSB <= ram_do[31:2];
|
else
|
else
|
if(MasterWbRX & m_wb_ack_i)
|
if(MasterWbRX & m_wb_ack_i)
|
RxPointerMSB <=#Tp RxPointerMSB + 1'b1; // Word access (always word access. m_wb_sel_o are used for selecting bytes)
|
RxPointerMSB <= RxPointerMSB + 1'b1; // Word access (always word access. m_wb_sel_o are used for selecting bytes)
|
end
|
end
|
|
|
|
|
//Latching last addresses from buffer descriptor (used as byte-half-word indicator);
|
//Latching last addresses from buffer descriptor (used as byte-half-word indicator);
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
RxPointerLSB_rst[1:0] <=#Tp 0;
|
RxPointerLSB_rst[1:0] <= 0;
|
else
|
else
|
if(MasterWbRX & m_wb_ack_i) // After first write all RxByteSel are active
|
if(MasterWbRX & m_wb_ack_i) // After first write all RxByteSel are active
|
RxPointerLSB_rst[1:0] <=#Tp 0;
|
RxPointerLSB_rst[1:0] <= 0;
|
else
|
else
|
if(RxEn & RxEn_q & RxPointerRead)
|
if(RxEn & RxEn_q & RxPointerRead)
|
RxPointerLSB_rst[1:0] <=#Tp ram_do[1:0];
|
RxPointerLSB_rst[1:0] <= ram_do[1:0];
|
end
|
end
|
|
|
|
|
always @ (RxPointerLSB_rst)
|
always @ (RxPointerLSB_rst)
|
begin
|
begin
|
| Line 1957... |
Line 1955... |
|
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
RxEn_needed <=#Tp 1'b0;
|
RxEn_needed <= 1'b0;
|
else
|
else
|
if(~RxReady & r_RxEn & WbEn & ~WbEn_q)
|
if(~RxReady & r_RxEn & WbEn & ~WbEn_q)
|
RxEn_needed <=#Tp 1'b1;
|
RxEn_needed <= 1'b1;
|
else
|
else
|
if(RxPointerRead & RxEn & RxEn_q)
|
if(RxPointerRead & RxEn & RxEn_q)
|
RxEn_needed <=#Tp 1'b0;
|
RxEn_needed <= 1'b0;
|
end
|
end
|
|
|
|
|
// Reception status is written back to the buffer descriptor after the end of frame is detected.
|
// Reception status is written back to the buffer descriptor after the end of frame is detected.
|
assign RxStatusWrite = ShiftEnded & RxEn & RxEn_q;
|
assign RxStatusWrite = ShiftEnded & RxEn & RxEn_q;
|
| Line 1976... |
Line 1974... |
|
|
// Indicating that last byte is being reveived
|
// Indicating that last byte is being reveived
|
always @ (posedge MRxClk or posedge Reset)
|
always @ (posedge MRxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
LastByteIn <=#Tp 1'b0;
|
LastByteIn <= 1'b0;
|
else
|
else
|
if(ShiftWillEnd & (&RxByteCnt) | RxAbort)
|
if(ShiftWillEnd & (&RxByteCnt) | RxAbort)
|
LastByteIn <=#Tp 1'b0;
|
LastByteIn <= 1'b0;
|
else
|
else
|
if(RxValid & RxReady & RxEndFrm & ~(&RxByteCnt) & RxEnableWindow)
|
if(RxValid & RxReady & RxEndFrm & ~(&RxByteCnt) & RxEnableWindow)
|
LastByteIn <=#Tp 1'b1;
|
LastByteIn <= 1'b1;
|
end
|
end
|
|
|
reg ShiftEnded_rck;
|
reg ShiftEnded_rck;
|
reg ShiftEndedSync1;
|
reg ShiftEndedSync1;
|
reg ShiftEndedSync2;
|
reg ShiftEndedSync2;
|
| Line 1999... |
Line 1997... |
|
|
// Indicating that data reception will end
|
// Indicating that data reception will end
|
always @ (posedge MRxClk or posedge Reset)
|
always @ (posedge MRxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
ShiftWillEnd <=#Tp 1'b0;
|
ShiftWillEnd <= 1'b0;
|
else
|
else
|
if(ShiftEnded_rck | RxAbort)
|
if(ShiftEnded_rck | RxAbort)
|
ShiftWillEnd <=#Tp 1'b0;
|
ShiftWillEnd <= 1'b0;
|
else
|
else
|
if(StartShiftWillEnd)
|
if(StartShiftWillEnd)
|
ShiftWillEnd <=#Tp 1'b1;
|
ShiftWillEnd <= 1'b1;
|
end
|
end
|
|
|
|
|
|
|
// Receive byte counter
|
// Receive byte counter
|
always @ (posedge MRxClk or posedge Reset)
|
always @ (posedge MRxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
RxByteCnt <=#Tp 2'h0;
|
RxByteCnt <= 2'h0;
|
else
|
else
|
if(ShiftEnded_rck | RxAbort)
|
if(ShiftEnded_rck | RxAbort)
|
RxByteCnt <=#Tp 2'h0;
|
RxByteCnt <= 2'h0;
|
else
|
else
|
if(RxValid & RxStartFrm & RxReady)
|
if(RxValid & RxStartFrm & RxReady)
|
case(RxPointerLSB_rst) // synopsys parallel_case
|
case(RxPointerLSB_rst) // synopsys parallel_case
|
2'h0 : RxByteCnt <=#Tp 2'h1;
|
2'h0 : RxByteCnt <= 2'h1;
|
2'h1 : RxByteCnt <=#Tp 2'h2;
|
2'h1 : RxByteCnt <= 2'h2;
|
2'h2 : RxByteCnt <=#Tp 2'h3;
|
2'h2 : RxByteCnt <= 2'h3;
|
2'h3 : RxByteCnt <=#Tp 2'h0;
|
2'h3 : RxByteCnt <= 2'h0;
|
endcase
|
endcase
|
else
|
else
|
if(RxValid & RxEnableWindow & RxReady | LastByteIn)
|
if(RxValid & RxEnableWindow & RxReady | LastByteIn)
|
RxByteCnt <=#Tp RxByteCnt + 1'b1;
|
RxByteCnt <= RxByteCnt + 1'b1;
|
end
|
end
|
|
|
|
|
// Indicates how many bytes are valid within the last word
|
// Indicates how many bytes are valid within the last word
|
always @ (posedge MRxClk or posedge Reset)
|
always @ (posedge MRxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
RxValidBytes <=#Tp 2'h1;
|
RxValidBytes <= 2'h1;
|
else
|
else
|
if(RxValid & RxStartFrm)
|
if(RxValid & RxStartFrm)
|
case(RxPointerLSB_rst) // synopsys parallel_case
|
case(RxPointerLSB_rst) // synopsys parallel_case
|
2'h0 : RxValidBytes <=#Tp 2'h1;
|
2'h0 : RxValidBytes <= 2'h1;
|
2'h1 : RxValidBytes <=#Tp 2'h2;
|
2'h1 : RxValidBytes <= 2'h2;
|
2'h2 : RxValidBytes <=#Tp 2'h3;
|
2'h2 : RxValidBytes <= 2'h3;
|
2'h3 : RxValidBytes <=#Tp 2'h0;
|
2'h3 : RxValidBytes <= 2'h0;
|
endcase
|
endcase
|
else
|
else
|
if(RxValid & ~LastByteIn & ~RxStartFrm & RxEnableWindow)
|
if(RxValid & ~LastByteIn & ~RxStartFrm & RxEnableWindow)
|
RxValidBytes <=#Tp RxValidBytes + 1'b1;
|
RxValidBytes <= RxValidBytes + 1'b1;
|
end
|
end
|
|
|
|
|
always @ (posedge MRxClk or posedge Reset)
|
always @ (posedge MRxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
RxDataLatched1 <=#Tp 24'h0;
|
RxDataLatched1 <= 24'h0;
|
else
|
else
|
if(RxValid & RxReady & ~LastByteIn)
|
if(RxValid & RxReady & ~LastByteIn)
|
if(RxStartFrm)
|
if(RxStartFrm)
|
begin
|
begin
|
case(RxPointerLSB_rst) // synopsys parallel_case
|
case(RxPointerLSB_rst) // synopsys parallel_case
|
2'h0: RxDataLatched1[31:24] <=#Tp RxData; // Big Endian Byte Ordering
|
2'h0: RxDataLatched1[31:24] <= RxData; // Big Endian Byte Ordering
|
2'h1: RxDataLatched1[23:16] <=#Tp RxData;
|
2'h1: RxDataLatched1[23:16] <= RxData;
|
2'h2: RxDataLatched1[15:8] <=#Tp RxData;
|
2'h2: RxDataLatched1[15:8] <= RxData;
|
2'h3: RxDataLatched1 <=#Tp RxDataLatched1;
|
2'h3: RxDataLatched1 <= RxDataLatched1;
|
endcase
|
endcase
|
end
|
end
|
else if (RxEnableWindow)
|
else if (RxEnableWindow)
|
begin
|
begin
|
case(RxByteCnt) // synopsys parallel_case
|
case(RxByteCnt) // synopsys parallel_case
|
2'h0: RxDataLatched1[31:24] <=#Tp RxData; // Big Endian Byte Ordering
|
2'h0: RxDataLatched1[31:24] <= RxData; // Big Endian Byte Ordering
|
2'h1: RxDataLatched1[23:16] <=#Tp RxData;
|
2'h1: RxDataLatched1[23:16] <= RxData;
|
2'h2: RxDataLatched1[15:8] <=#Tp RxData;
|
2'h2: RxDataLatched1[15:8] <= RxData;
|
2'h3: RxDataLatched1 <=#Tp RxDataLatched1;
|
2'h3: RxDataLatched1 <= RxDataLatched1;
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
|
|
wire SetWriteRxDataToFifo;
|
wire SetWriteRxDataToFifo;
|
|
|
// Assembling data that will be written to the rx_fifo
|
// Assembling data that will be written to the rx_fifo
|
always @ (posedge MRxClk or posedge Reset)
|
always @ (posedge MRxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
RxDataLatched2 <=#Tp 32'h0;
|
RxDataLatched2 <= 32'h0;
|
else
|
else
|
if(SetWriteRxDataToFifo & ~ShiftWillEnd)
|
if(SetWriteRxDataToFifo & ~ShiftWillEnd)
|
RxDataLatched2 <=#Tp {RxDataLatched1[31:8], RxData}; // Big Endian Byte Ordering
|
RxDataLatched2 <= {RxDataLatched1[31:8], RxData}; // Big Endian Byte Ordering
|
else
|
else
|
if(SetWriteRxDataToFifo & ShiftWillEnd)
|
if(SetWriteRxDataToFifo & ShiftWillEnd)
|
case(RxValidBytes) // synopsys parallel_case
|
case(RxValidBytes) // synopsys parallel_case
|
0 : RxDataLatched2 <=#Tp {RxDataLatched1[31:8], RxData}; // Big Endian Byte Ordering
|
0 : RxDataLatched2 <= {RxDataLatched1[31:8], RxData}; // Big Endian Byte Ordering
|
1 : RxDataLatched2 <=#Tp {RxDataLatched1[31:24], 24'h0};
|
1 : RxDataLatched2 <= {RxDataLatched1[31:24], 24'h0};
|
2 : RxDataLatched2 <=#Tp {RxDataLatched1[31:16], 16'h0};
|
2 : RxDataLatched2 <= {RxDataLatched1[31:16], 16'h0};
|
3 : RxDataLatched2 <=#Tp {RxDataLatched1[31:8], 8'h0};
|
3 : RxDataLatched2 <= {RxDataLatched1[31:8], 8'h0};
|
endcase
|
endcase
|
end
|
end
|
|
|
|
|
reg WriteRxDataToFifoSync1;
|
reg WriteRxDataToFifoSync1;
|
| Line 2111... |
Line 2109... |
(ShiftWillEnd & LastByteIn & (&RxByteCnt));
|
(ShiftWillEnd & LastByteIn & (&RxByteCnt));
|
|
|
always @ (posedge MRxClk or posedge Reset)
|
always @ (posedge MRxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
WriteRxDataToFifo <=#Tp 1'b0;
|
WriteRxDataToFifo <= 1'b0;
|
else
|
else
|
if(SetWriteRxDataToFifo & ~RxAbort)
|
if(SetWriteRxDataToFifo & ~RxAbort)
|
WriteRxDataToFifo <=#Tp 1'b1;
|
WriteRxDataToFifo <= 1'b1;
|
else
|
else
|
if(WriteRxDataToFifoSync2 | RxAbort)
|
if(WriteRxDataToFifoSync2 | RxAbort)
|
WriteRxDataToFifo <=#Tp 1'b0;
|
WriteRxDataToFifo <= 1'b0;
|
end
|
end
|
|
|
|
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
WriteRxDataToFifoSync1 <=#Tp 1'b0;
|
WriteRxDataToFifoSync1 <= 1'b0;
|
else
|
else
|
if(WriteRxDataToFifo)
|
if(WriteRxDataToFifo)
|
WriteRxDataToFifoSync1 <=#Tp 1'b1;
|
WriteRxDataToFifoSync1 <= 1'b1;
|
else
|
else
|
WriteRxDataToFifoSync1 <=#Tp 1'b0;
|
WriteRxDataToFifoSync1 <= 1'b0;
|
end
|
end
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
WriteRxDataToFifoSync2 <=#Tp 1'b0;
|
WriteRxDataToFifoSync2 <= 1'b0;
|
else
|
else
|
WriteRxDataToFifoSync2 <=#Tp WriteRxDataToFifoSync1;
|
WriteRxDataToFifoSync2 <= WriteRxDataToFifoSync1;
|
end
|
end
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
WriteRxDataToFifoSync3 <=#Tp 1'b0;
|
WriteRxDataToFifoSync3 <= 1'b0;
|
else
|
else
|
WriteRxDataToFifoSync3 <=#Tp WriteRxDataToFifoSync2;
|
WriteRxDataToFifoSync3 <= WriteRxDataToFifoSync2;
|
end
|
end
|
|
|
wire WriteRxDataToFifo_wb;
|
wire WriteRxDataToFifo_wb;
|
assign WriteRxDataToFifo_wb = WriteRxDataToFifoSync2 & ~WriteRxDataToFifoSync3;
|
assign WriteRxDataToFifo_wb = WriteRxDataToFifoSync2 & ~WriteRxDataToFifoSync3;
|
|
|
| Line 2162... |
Line 2160... |
wire RxFifoReset;
|
wire RxFifoReset;
|
|
|
always @ (posedge MRxClk or posedge Reset)
|
always @ (posedge MRxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
LatchedRxStartFrm <=#Tp 0;
|
LatchedRxStartFrm <= 0;
|
else
|
else
|
if(RxStartFrm & ~SyncRxStartFrm_q)
|
if(RxStartFrm & ~SyncRxStartFrm_q)
|
LatchedRxStartFrm <=#Tp 1;
|
LatchedRxStartFrm <= 1;
|
else
|
else
|
if(SyncRxStartFrm_q)
|
if(SyncRxStartFrm_q)
|
LatchedRxStartFrm <=#Tp 0;
|
LatchedRxStartFrm <= 0;
|
end
|
end
|
|
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
SyncRxStartFrm <=#Tp 0;
|
SyncRxStartFrm <= 0;
|
else
|
else
|
if(LatchedRxStartFrm)
|
if(LatchedRxStartFrm)
|
SyncRxStartFrm <=#Tp 1;
|
SyncRxStartFrm <= 1;
|
else
|
else
|
SyncRxStartFrm <=#Tp 0;
|
SyncRxStartFrm <= 0;
|
end
|
end
|
|
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
SyncRxStartFrm_q <=#Tp 0;
|
SyncRxStartFrm_q <= 0;
|
else
|
else
|
SyncRxStartFrm_q <=#Tp SyncRxStartFrm;
|
SyncRxStartFrm_q <= SyncRxStartFrm;
|
end
|
end
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
SyncRxStartFrm_q2 <=#Tp 0;
|
SyncRxStartFrm_q2 <= 0;
|
else
|
else
|
SyncRxStartFrm_q2 <=#Tp SyncRxStartFrm_q;
|
SyncRxStartFrm_q2 <= SyncRxStartFrm_q;
|
end
|
end
|
|
|
|
|
assign RxFifoReset = SyncRxStartFrm_q & ~SyncRxStartFrm_q2;
|
assign RxFifoReset = SyncRxStartFrm_q & ~SyncRxStartFrm_q2;
|
|
|
eth_fifo #(.DATA_WIDTH(RX_FIFO_DATA_WIDTH),
|
eth_fifo #(.DATA_WIDTH(RX_FIFO_DATA_WIDTH),
|
.DEPTH(RX_FIFO_DEPTH),
|
.DEPTH(RX_FIFO_DEPTH),
|
.CNT_WIDTH(RX_FIFO_CNT_WIDTH),
|
.CNT_WIDTH(RX_FIFO_CNT_WIDTH))
|
.Tp(Tp))
|
|
rx_fifo (.data_in(RxDataLatched2), .data_out(m_wb_dat_o),
|
rx_fifo (.data_in(RxDataLatched2), .data_out(m_wb_dat_o),
|
.clk(WB_CLK_I), .reset(Reset),
|
.clk(WB_CLK_I), .reset(Reset),
|
.write(WriteRxDataToFifo_wb & ~RxBufferFull), .read(MasterWbRX & m_wb_ack_i),
|
.write(WriteRxDataToFifo_wb & ~RxBufferFull), .read(MasterWbRX & m_wb_ack_i),
|
.clear(RxFifoReset), .full(RxBufferFull),
|
.clear(RxFifoReset), .full(RxBufferFull),
|
.almost_full(), .almost_empty(RxBufferAlmostEmpty),
|
.almost_full(), .almost_empty(RxBufferAlmostEmpty),
|
| Line 2225... |
Line 2222... |
|
|
// Generation of the end-of-frame signal
|
// Generation of the end-of-frame signal
|
always @ (posedge MRxClk or posedge Reset)
|
always @ (posedge MRxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
ShiftEnded_rck <=#Tp 1'b0;
|
ShiftEnded_rck <= 1'b0;
|
else
|
else
|
if(~RxAbort & SetWriteRxDataToFifo & StartShiftWillEnd)
|
if(~RxAbort & SetWriteRxDataToFifo & StartShiftWillEnd)
|
ShiftEnded_rck <=#Tp 1'b1;
|
ShiftEnded_rck <= 1'b1;
|
else
|
else
|
if(RxAbort | ShiftEndedSync_c1 & ShiftEndedSync_c2)
|
if(RxAbort | ShiftEndedSync_c1 & ShiftEndedSync_c2)
|
ShiftEnded_rck <=#Tp 1'b0;
|
ShiftEnded_rck <= 1'b0;
|
end
|
end
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
ShiftEndedSync1 <=#Tp 1'b0;
|
ShiftEndedSync1 <= 1'b0;
|
else
|
else
|
ShiftEndedSync1 <=#Tp ShiftEnded_rck;
|
ShiftEndedSync1 <= ShiftEnded_rck;
|
end
|
end
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
ShiftEndedSync2 <=#Tp 1'b0;
|
ShiftEndedSync2 <= 1'b0;
|
else
|
else
|
ShiftEndedSync2 <=#Tp ShiftEndedSync1;
|
ShiftEndedSync2 <= ShiftEndedSync1;
|
end
|
end
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
ShiftEndedSync3 <=#Tp 1'b0;
|
ShiftEndedSync3 <= 1'b0;
|
else
|
else
|
if(ShiftEndedSync1 & ~ShiftEndedSync2)
|
if(ShiftEndedSync1 & ~ShiftEndedSync2)
|
ShiftEndedSync3 <=#Tp 1'b1;
|
ShiftEndedSync3 <= 1'b1;
|
else
|
else
|
if(ShiftEnded)
|
if(ShiftEnded)
|
ShiftEndedSync3 <=#Tp 1'b0;
|
ShiftEndedSync3 <= 1'b0;
|
end
|
end
|
|
|
// Generation of the end-of-frame signal
|
// Generation of the end-of-frame signal
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
ShiftEnded <=#Tp 1'b0;
|
ShiftEnded <= 1'b0;
|
else
|
else
|
if(ShiftEndedSync3 & MasterWbRX & m_wb_ack_i & RxBufferAlmostEmpty & ~ShiftEnded)
|
if(ShiftEndedSync3 & MasterWbRX & m_wb_ack_i & RxBufferAlmostEmpty & ~ShiftEnded)
|
ShiftEnded <=#Tp 1'b1;
|
ShiftEnded <= 1'b1;
|
else
|
else
|
if(RxStatusWrite)
|
if(RxStatusWrite)
|
ShiftEnded <=#Tp 1'b0;
|
ShiftEnded <= 1'b0;
|
end
|
end
|
|
|
always @ (posedge MRxClk or posedge Reset)
|
always @ (posedge MRxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
ShiftEndedSync_c1 <=#Tp 1'b0;
|
ShiftEndedSync_c1 <= 1'b0;
|
else
|
else
|
ShiftEndedSync_c1 <=#Tp ShiftEndedSync2;
|
ShiftEndedSync_c1 <= ShiftEndedSync2;
|
end
|
end
|
|
|
always @ (posedge MRxClk or posedge Reset)
|
always @ (posedge MRxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
ShiftEndedSync_c2 <=#Tp 1'b0;
|
ShiftEndedSync_c2 <= 1'b0;
|
else
|
else
|
ShiftEndedSync_c2 <=#Tp ShiftEndedSync_c1;
|
ShiftEndedSync_c2 <= ShiftEndedSync_c1;
|
end
|
end
|
|
|
// Generation of the end-of-frame signal
|
// Generation of the end-of-frame signal
|
always @ (posedge MRxClk or posedge Reset)
|
always @ (posedge MRxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
RxEnableWindow <=#Tp 1'b0;
|
RxEnableWindow <= 1'b0;
|
else
|
else
|
if(RxStartFrm)
|
if(RxStartFrm)
|
RxEnableWindow <=#Tp 1'b1;
|
RxEnableWindow <= 1'b1;
|
else
|
else
|
if(RxEndFrm | RxAbort)
|
if(RxEndFrm | RxAbort)
|
RxEnableWindow <=#Tp 1'b0;
|
RxEnableWindow <= 1'b0;
|
end
|
end
|
|
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
RxAbortSync1 <=#Tp 1'b0;
|
RxAbortSync1 <= 1'b0;
|
else
|
else
|
RxAbortSync1 <=#Tp RxAbortLatched;
|
RxAbortSync1 <= RxAbortLatched;
|
end
|
end
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
RxAbortSync2 <=#Tp 1'b0;
|
RxAbortSync2 <= 1'b0;
|
else
|
else
|
RxAbortSync2 <=#Tp RxAbortSync1;
|
RxAbortSync2 <= RxAbortSync1;
|
end
|
end
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
RxAbortSync3 <=#Tp 1'b0;
|
RxAbortSync3 <= 1'b0;
|
else
|
else
|
RxAbortSync3 <=#Tp RxAbortSync2;
|
RxAbortSync3 <= RxAbortSync2;
|
end
|
end
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
RxAbortSync4 <=#Tp 1'b0;
|
RxAbortSync4 <= 1'b0;
|
else
|
else
|
RxAbortSync4 <=#Tp RxAbortSync3;
|
RxAbortSync4 <= RxAbortSync3;
|
end
|
end
|
|
|
always @ (posedge MRxClk or posedge Reset)
|
always @ (posedge MRxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
RxAbortSyncb1 <=#Tp 1'b0;
|
RxAbortSyncb1 <= 1'b0;
|
else
|
else
|
RxAbortSyncb1 <=#Tp RxAbortSync2;
|
RxAbortSyncb1 <= RxAbortSync2;
|
end
|
end
|
|
|
always @ (posedge MRxClk or posedge Reset)
|
always @ (posedge MRxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
RxAbortSyncb2 <=#Tp 1'b0;
|
RxAbortSyncb2 <= 1'b0;
|
else
|
else
|
RxAbortSyncb2 <=#Tp RxAbortSyncb1;
|
RxAbortSyncb2 <= RxAbortSyncb1;
|
end
|
end
|
|
|
|
|
always @ (posedge MRxClk or posedge Reset)
|
always @ (posedge MRxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
RxAbortLatched <=#Tp 1'b0;
|
RxAbortLatched <= 1'b0;
|
else
|
else
|
if(RxAbortSyncb2)
|
if(RxAbortSyncb2)
|
RxAbortLatched <=#Tp 1'b0;
|
RxAbortLatched <= 1'b0;
|
else
|
else
|
if(RxAbort)
|
if(RxAbort)
|
RxAbortLatched <=#Tp 1'b1;
|
RxAbortLatched <= 1'b1;
|
end
|
end
|
|
|
|
|
always @ (posedge MRxClk or posedge Reset)
|
always @ (posedge MRxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
LatchedRxLength[15:0] <=#Tp 16'h0;
|
LatchedRxLength[15:0] <= 16'h0;
|
else
|
else
|
if(LoadRxStatus)
|
if(LoadRxStatus)
|
LatchedRxLength[15:0] <=#Tp RxLength[15:0];
|
LatchedRxLength[15:0] <= RxLength[15:0];
|
end
|
end
|
|
|
|
|
assign RxStatusIn = {ReceivedPauseFrm, AddressMiss, RxOverrun, InvalidSymbol, DribbleNibble, ReceivedPacketTooBig, ShortFrame, LatchedCrcError, RxLateCollision};
|
assign RxStatusIn = {ReceivedPauseFrm, AddressMiss, RxOverrun, InvalidSymbol, DribbleNibble, ReceivedPacketTooBig, ShortFrame, LatchedCrcError, RxLateCollision};
|
|
|
always @ (posedge MRxClk or posedge Reset)
|
always @ (posedge MRxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
RxStatusInLatched <=#Tp 'h0;
|
RxStatusInLatched <= 'h0;
|
else
|
else
|
if(LoadRxStatus)
|
if(LoadRxStatus)
|
RxStatusInLatched <=#Tp RxStatusIn;
|
RxStatusInLatched <= RxStatusIn;
|
end
|
end
|
|
|
|
|
// Rx overrun
|
// Rx overrun
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
RxOverrun <=#Tp 1'b0;
|
RxOverrun <= 1'b0;
|
else
|
else
|
if(RxStatusWrite)
|
if(RxStatusWrite)
|
RxOverrun <=#Tp 1'b0;
|
RxOverrun <= 1'b0;
|
else
|
else
|
if(RxBufferFull & WriteRxDataToFifo_wb)
|
if(RxBufferFull & WriteRxDataToFifo_wb)
|
RxOverrun <=#Tp 1'b1;
|
RxOverrun <= 1'b1;
|
end
|
end
|
|
|
|
|
|
|
wire TxError;
|
wire TxError;
|
| Line 2428... |
Line 2425... |
|
|
// Latching and synchronizing RxStatusWrite signal. This signal is used for clearing the ReceivedPauseFrm signal
|
// Latching and synchronizing RxStatusWrite signal. This signal is used for clearing the ReceivedPauseFrm signal
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
RxStatusWriteLatched <=#Tp 1'b0;
|
RxStatusWriteLatched <= 1'b0;
|
else
|
else
|
if(RxStatusWriteLatched_syncb2)
|
if(RxStatusWriteLatched_syncb2)
|
RxStatusWriteLatched <=#Tp 1'b0;
|
RxStatusWriteLatched <= 1'b0;
|
else
|
else
|
if(RxStatusWrite)
|
if(RxStatusWrite)
|
RxStatusWriteLatched <=#Tp 1'b1;
|
RxStatusWriteLatched <= 1'b1;
|
end
|
end
|
|
|
|
|
always @ (posedge MRxClk or posedge Reset)
|
always @ (posedge MRxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
begin
|
begin
|
RxStatusWriteLatched_sync1 <=#Tp 1'b0;
|
RxStatusWriteLatched_sync1 <= 1'b0;
|
RxStatusWriteLatched_sync2 <=#Tp 1'b0;
|
RxStatusWriteLatched_sync2 <= 1'b0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
RxStatusWriteLatched_sync1 <=#Tp RxStatusWriteLatched;
|
RxStatusWriteLatched_sync1 <= RxStatusWriteLatched;
|
RxStatusWriteLatched_sync2 <=#Tp RxStatusWriteLatched_sync1;
|
RxStatusWriteLatched_sync2 <= RxStatusWriteLatched_sync1;
|
end
|
end
|
end
|
end
|
|
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
begin
|
begin
|
RxStatusWriteLatched_syncb1 <=#Tp 1'b0;
|
RxStatusWriteLatched_syncb1 <= 1'b0;
|
RxStatusWriteLatched_syncb2 <=#Tp 1'b0;
|
RxStatusWriteLatched_syncb2 <= 1'b0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
RxStatusWriteLatched_syncb1 <=#Tp RxStatusWriteLatched_sync2;
|
RxStatusWriteLatched_syncb1 <= RxStatusWriteLatched_sync2;
|
RxStatusWriteLatched_syncb2 <=#Tp RxStatusWriteLatched_syncb1;
|
RxStatusWriteLatched_syncb2 <= RxStatusWriteLatched_syncb1;
|
end
|
end
|
end
|
end
|
|
|
|
|
|
|
// Tx Done Interrupt
|
// Tx Done Interrupt
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
TxB_IRQ <=#Tp 1'b0;
|
TxB_IRQ <= 1'b0;
|
else
|
else
|
if(TxStatusWrite & TxIRQEn)
|
if(TxStatusWrite & TxIRQEn)
|
TxB_IRQ <=#Tp ~TxError;
|
TxB_IRQ <= ~TxError;
|
else
|
else
|
TxB_IRQ <=#Tp 1'b0;
|
TxB_IRQ <= 1'b0;
|
end
|
end
|
|
|
|
|
// Tx Error Interrupt
|
// Tx Error Interrupt
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
TxE_IRQ <=#Tp 1'b0;
|
TxE_IRQ <= 1'b0;
|
else
|
else
|
if(TxStatusWrite & TxIRQEn)
|
if(TxStatusWrite & TxIRQEn)
|
TxE_IRQ <=#Tp TxError;
|
TxE_IRQ <= TxError;
|
else
|
else
|
TxE_IRQ <=#Tp 1'b0;
|
TxE_IRQ <= 1'b0;
|
end
|
end
|
|
|
|
|
// Rx Done Interrupt
|
// Rx Done Interrupt
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
RxB_IRQ <=#Tp 1'b0;
|
RxB_IRQ <= 1'b0;
|
else
|
else
|
if(RxStatusWrite & RxIRQEn & ReceivedPacketGood & (~ReceivedPauseFrm | ReceivedPauseFrm & r_PassAll & (~r_RxFlow)))
|
if(RxStatusWrite & RxIRQEn & ReceivedPacketGood & (~ReceivedPauseFrm | ReceivedPauseFrm & r_PassAll & (~r_RxFlow)))
|
RxB_IRQ <=#Tp (~RxError);
|
RxB_IRQ <= (~RxError);
|
else
|
else
|
RxB_IRQ <=#Tp 1'b0;
|
RxB_IRQ <= 1'b0;
|
end
|
end
|
|
|
|
|
// Rx Error Interrupt
|
// Rx Error Interrupt
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
RxE_IRQ <=#Tp 1'b0;
|
RxE_IRQ <= 1'b0;
|
else
|
else
|
if(RxStatusWrite & RxIRQEn & (~ReceivedPauseFrm | ReceivedPauseFrm & r_PassAll & (~r_RxFlow)))
|
if(RxStatusWrite & RxIRQEn & (~ReceivedPauseFrm | ReceivedPauseFrm & r_PassAll & (~r_RxFlow)))
|
RxE_IRQ <=#Tp RxError;
|
RxE_IRQ <= RxError;
|
else
|
else
|
RxE_IRQ <=#Tp 1'b0;
|
RxE_IRQ <= 1'b0;
|
end
|
end
|
|
|
|
|
// Busy Interrupt
|
// Busy Interrupt
|
|
|
| Line 2534... |
Line 2531... |
|
|
|
|
always @ (posedge MRxClk or posedge Reset)
|
always @ (posedge MRxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
Busy_IRQ_rck <=#Tp 1'b0;
|
Busy_IRQ_rck <= 1'b0;
|
else
|
else
|
if(RxValid & RxStartFrm & ~RxReady)
|
if(RxValid & RxStartFrm & ~RxReady)
|
Busy_IRQ_rck <=#Tp 1'b1;
|
Busy_IRQ_rck <= 1'b1;
|
else
|
else
|
if(Busy_IRQ_syncb2)
|
if(Busy_IRQ_syncb2)
|
Busy_IRQ_rck <=#Tp 1'b0;
|
Busy_IRQ_rck <= 1'b0;
|
end
|
end
|
|
|
always @ (posedge WB_CLK_I)
|
always @ (posedge WB_CLK_I)
|
begin
|
begin
|
Busy_IRQ_sync1 <=#Tp Busy_IRQ_rck;
|
Busy_IRQ_sync1 <= Busy_IRQ_rck;
|
Busy_IRQ_sync2 <=#Tp Busy_IRQ_sync1;
|
Busy_IRQ_sync2 <= Busy_IRQ_sync1;
|
Busy_IRQ_sync3 <=#Tp Busy_IRQ_sync2;
|
Busy_IRQ_sync3 <= Busy_IRQ_sync2;
|
end
|
end
|
|
|
always @ (posedge MRxClk)
|
always @ (posedge MRxClk)
|
begin
|
begin
|
Busy_IRQ_syncb1 <=#Tp Busy_IRQ_sync2;
|
Busy_IRQ_syncb1 <= Busy_IRQ_sync2;
|
Busy_IRQ_syncb2 <=#Tp Busy_IRQ_syncb1;
|
Busy_IRQ_syncb2 <= Busy_IRQ_syncb1;
|
end
|
end
|
|
|
assign Busy_IRQ = Busy_IRQ_sync2 & ~Busy_IRQ_sync3;
|
assign Busy_IRQ = Busy_IRQ_sync2 & ~Busy_IRQ_sync3;
|
|
|
|
|
