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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_wishbone.v] - Diff between revs 360 and 367

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Rev 360 Rev 367
Line 266... Line 266...
   // WISHBONE master
   // WISHBONE master
   m_wb_adr_o, m_wb_sel_o, m_wb_we_o,
   m_wb_adr_o, m_wb_sel_o, m_wb_we_o,
   m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,
   m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,
   m_wb_stb_o, m_wb_ack_i, m_wb_err_i,
   m_wb_stb_o, m_wb_ack_i, m_wb_err_i,
 
 
`ifdef ETH_WISHBONE_B3
 
   m_wb_cti_o, m_wb_bte_o,
   m_wb_cti_o, m_wb_bte_o,
`endif
 
 
 
   //TX
   //TX
   MTxClk, TxStartFrm, TxEndFrm, TxUsedData, TxData,
   MTxClk, TxStartFrm, TxEndFrm, TxUsedData, TxData,
   TxRetry, TxAbort, TxUnderRun, TxDone, PerPacketCrcEn,
   TxRetry, TxAbort, TxUnderRun, TxDone, PerPacketCrcEn,
   PerPacketPad,
   PerPacketPad,
Line 341... Line 339...
output          m_wb_stb_o;     // 
output          m_wb_stb_o;     // 
input   [31:0]  m_wb_dat_i;     // 
input   [31:0]  m_wb_dat_i;     // 
input           m_wb_ack_i;     // 
input           m_wb_ack_i;     // 
input           m_wb_err_i;     // 
input           m_wb_err_i;     // 
 
 
`ifdef ETH_WISHBONE_B3
 
output   [2:0]  m_wb_cti_o;     // Cycle Type Identifier
output   [2:0]  m_wb_cti_o;     // Cycle Type Identifier
output   [1:0]  m_wb_bte_o;     // Burst Type Extension
output   [1:0]  m_wb_bte_o;     // Burst Type Extension
reg      [2:0]  m_wb_cti_o;     // Cycle Type Identifier
reg      [2:0]  m_wb_cti_o;     // Cycle Type Identifier
`endif
 
 
 
input           Reset;       // Reset signal
input           Reset;       // Reset signal
 
 
// Rx Status signals
// Rx Status signals
input           InvalidSymbol;    // Invalid symbol was received during reception in 100 Mbps mode
input           InvalidSymbol;    // Invalid symbol was received during reception in 100 Mbps mode
Line 687... Line 683...
reg RxStatusWriteLatched_sync1;
reg RxStatusWriteLatched_sync1;
reg RxStatusWriteLatched_sync2;
reg RxStatusWriteLatched_sync2;
reg RxStatusWriteLatched_syncb1;
reg RxStatusWriteLatched_syncb1;
reg RxStatusWriteLatched_syncb2;
reg RxStatusWriteLatched_syncb2;
 
 
`ifdef ETH_WISHBONE_B3
 
assign m_wb_bte_o = 2'b00;    // Linear burst
assign m_wb_bte_o = 2'b00;    // Linear burst
`endif
 
 
 
assign m_wb_stb_o = m_wb_cyc_o;
assign m_wb_stb_o = m_wb_cyc_o;
 
 
always @ (posedge WB_CLK_I)
always @ (posedge WB_CLK_I)
begin
begin
Line 1142... Line 1136...
      tx_burst_cnt<= 0;
      tx_burst_cnt<= 0;
      rx_burst_cnt<= 0;
      rx_burst_cnt<= 0;
      IncrTxPointer<= 1'b0;
      IncrTxPointer<= 1'b0;
      tx_burst_en<= 1'b1;
      tx_burst_en<= 1'b1;
      rx_burst_en<= 1'b0;
      rx_burst_en<= 1'b0;
`ifdef ETH_WISHBONE_B3
 
      m_wb_cti_o <= 3'b0;
      m_wb_cti_o <= 3'b0;
`endif
 
    end
    end
  else
  else
    begin
    begin
      // Switching between two stages depends on enable signals
      // Switching between two stages depends on enable signals
      casez ({MasterWbTX,
      casez ({MasterWbTX,
Line 1178... Line 1170...
            else
            else
              m_wb_adr_o <= m_wb_adr_o + 1'b1;
              m_wb_adr_o <= m_wb_adr_o + 1'b1;
            if(tx_burst_cnt==(`ETH_BURST_LENGTH-1))
            if(tx_burst_cnt==(`ETH_BURST_LENGTH-1))
              begin
              begin
                tx_burst_en<= 1'b0;
                tx_burst_en<= 1'b0;
`ifdef ETH_WISHBONE_B3
 
                m_wb_cti_o <= 3'b111;
                m_wb_cti_o <= 3'b111;
`endif
 
              end
              end
            else
            else
              begin
              begin
`ifdef ETH_WISHBONE_B3
 
                m_wb_cti_o <= 3'b010;
                m_wb_cti_o <= 3'b010;
`endif
 
              end
              end
          end
          end
        8'b00_?1_00_?1,             // Idle and MWB needed
        8'b00_?1_00_?1,             // Idle and MWB needed
        8'b01_?1_10_?1,             // MWB continues
        8'b01_?1_10_?1,             // MWB continues
        8'b01_01_01_01,             // Clear (previously MW) and MWB needed
        8'b01_01_01_01,             // Clear (previously MW) and MWB needed
Line 1211... Line 1199...
              m_wb_adr_o <= m_wb_adr_o+1'b1;
              m_wb_adr_o <= m_wb_adr_o+1'b1;
 
 
            if(rx_burst_cnt==(`ETH_BURST_LENGTH-1))
            if(rx_burst_cnt==(`ETH_BURST_LENGTH-1))
              begin
              begin
                rx_burst_en<= 1'b0;
                rx_burst_en<= 1'b0;
 `ifdef ETH_WISHBONE_B3
 
                m_wb_cti_o <= 3'b111;
                m_wb_cti_o <= 3'b111;
 `endif
 
              end
              end
            else
            else
              begin
              begin
 `ifdef ETH_WISHBONE_B3
 
                m_wb_cti_o <= 3'b010;
                m_wb_cti_o <= 3'b010;
 `endif
 
              end
              end
          end
          end
        8'b00_?1_00_?0 :// idle and MW is needed (data write to rx buffer)
        8'b00_?1_00_?0 :// idle and MW is needed (data write to rx buffer)
          begin
          begin
            MasterWbTX <= 1'b0;
            MasterWbTX <= 1'b0;
Line 1284... Line 1268...
            IncrTxPointer<= 1'b0;
            IncrTxPointer<= 1'b0;
            tx_burst_cnt<= 0;
            tx_burst_cnt<= 0;
            tx_burst_en<= txfifo_cnt<(TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4));
            tx_burst_en<= txfifo_cnt<(TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4));
            rx_burst_cnt<= 0;
            rx_burst_cnt<= 0;
            rx_burst_en<= MasterWbRX ? enough_data_in_rxfifo_for_burst_plus1 : enough_data_in_rxfifo_for_burst;  // Counter is not decremented, yet, so plus1 is used.
            rx_burst_en<= MasterWbRX ? enough_data_in_rxfifo_for_burst_plus1 : enough_data_in_rxfifo_for_burst;  // Counter is not decremented, yet, so plus1 is used.
`ifdef ETH_WISHBONE_B3
 
              m_wb_cti_o <= 3'b0;
              m_wb_cti_o <= 3'b0;
`endif
 
          end
          end
        8'b??_00_10_00,// whatever and no master read or write is needed
        8'b??_00_10_00,// whatever and no master read or write is needed
                       // (ack or err comes finishing previous access)
                       // (ack or err comes finishing previous access)
        8'b??_00_01_00 : // Between cyc_cleared request was cleared
        8'b??_00_01_00 : // Between cyc_cleared request was cleared
          begin
          begin
Line 1301... Line 1283...
            IncrTxPointer<= 1'b0;
            IncrTxPointer<= 1'b0;
            rx_burst_cnt<= 0;
            rx_burst_cnt<= 0;
            // Counter is not decremented, yet, so plus1 is used.
            // Counter is not decremented, yet, so plus1 is used.
            rx_burst_en<= MasterWbRX ? enough_data_in_rxfifo_for_burst_plus1 :
            rx_burst_en<= MasterWbRX ? enough_data_in_rxfifo_for_burst_plus1 :
                                       enough_data_in_rxfifo_for_burst;
                                       enough_data_in_rxfifo_for_burst;
`ifdef ETH_WISHBONE_B3
 
            m_wb_cti_o <= 3'b0;
            m_wb_cti_o <= 3'b0;
`endif
 
          end
          end
        8'b00_00_00_00:  // whatever and no master read or write is needed
        8'b00_00_00_00:  // whatever and no master read or write is needed
                         // (ack or err comes finishing previous access)
                         // (ack or err comes finishing previous access)
          begin
          begin
            tx_burst_cnt<= 0;
            tx_burst_cnt<= 0;

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