| Line 266... |
Line 266... |
// WISHBONE master
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// WISHBONE master
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m_wb_adr_o, m_wb_sel_o, m_wb_we_o,
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m_wb_adr_o, m_wb_sel_o, m_wb_we_o,
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m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,
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m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,
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m_wb_stb_o, m_wb_ack_i, m_wb_err_i,
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m_wb_stb_o, m_wb_ack_i, m_wb_err_i,
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|
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`ifdef ETH_WISHBONE_B3
|
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m_wb_cti_o, m_wb_bte_o,
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m_wb_cti_o, m_wb_bte_o,
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`endif
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|
|
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//TX
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//TX
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MTxClk, TxStartFrm, TxEndFrm, TxUsedData, TxData,
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MTxClk, TxStartFrm, TxEndFrm, TxUsedData, TxData,
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TxRetry, TxAbort, TxUnderRun, TxDone, PerPacketCrcEn,
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TxRetry, TxAbort, TxUnderRun, TxDone, PerPacketCrcEn,
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PerPacketPad,
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PerPacketPad,
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| Line 341... |
Line 339... |
output m_wb_stb_o; //
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output m_wb_stb_o; //
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input [31:0] m_wb_dat_i; //
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input [31:0] m_wb_dat_i; //
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input m_wb_ack_i; //
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input m_wb_ack_i; //
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input m_wb_err_i; //
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input m_wb_err_i; //
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|
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`ifdef ETH_WISHBONE_B3
|
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output [2:0] m_wb_cti_o; // Cycle Type Identifier
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output [2:0] m_wb_cti_o; // Cycle Type Identifier
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output [1:0] m_wb_bte_o; // Burst Type Extension
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output [1:0] m_wb_bte_o; // Burst Type Extension
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reg [2:0] m_wb_cti_o; // Cycle Type Identifier
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reg [2:0] m_wb_cti_o; // Cycle Type Identifier
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`endif
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|
|
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input Reset; // Reset signal
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input Reset; // Reset signal
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|
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// Rx Status signals
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// Rx Status signals
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input InvalidSymbol; // Invalid symbol was received during reception in 100 Mbps mode
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input InvalidSymbol; // Invalid symbol was received during reception in 100 Mbps mode
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| Line 687... |
Line 683... |
reg RxStatusWriteLatched_sync1;
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reg RxStatusWriteLatched_sync1;
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reg RxStatusWriteLatched_sync2;
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reg RxStatusWriteLatched_sync2;
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reg RxStatusWriteLatched_syncb1;
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reg RxStatusWriteLatched_syncb1;
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reg RxStatusWriteLatched_syncb2;
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reg RxStatusWriteLatched_syncb2;
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|
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`ifdef ETH_WISHBONE_B3
|
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assign m_wb_bte_o = 2'b00; // Linear burst
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assign m_wb_bte_o = 2'b00; // Linear burst
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`endif
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|
|
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assign m_wb_stb_o = m_wb_cyc_o;
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assign m_wb_stb_o = m_wb_cyc_o;
|
|
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always @ (posedge WB_CLK_I)
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always @ (posedge WB_CLK_I)
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begin
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begin
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| Line 1142... |
Line 1136... |
tx_burst_cnt<= 0;
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tx_burst_cnt<= 0;
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rx_burst_cnt<= 0;
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rx_burst_cnt<= 0;
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IncrTxPointer<= 1'b0;
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IncrTxPointer<= 1'b0;
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tx_burst_en<= 1'b1;
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tx_burst_en<= 1'b1;
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rx_burst_en<= 1'b0;
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rx_burst_en<= 1'b0;
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`ifdef ETH_WISHBONE_B3
|
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m_wb_cti_o <= 3'b0;
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m_wb_cti_o <= 3'b0;
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`endif
|
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end
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end
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else
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else
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begin
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begin
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// Switching between two stages depends on enable signals
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// Switching between two stages depends on enable signals
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casez ({MasterWbTX,
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casez ({MasterWbTX,
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| Line 1178... |
Line 1170... |
else
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else
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m_wb_adr_o <= m_wb_adr_o + 1'b1;
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m_wb_adr_o <= m_wb_adr_o + 1'b1;
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if(tx_burst_cnt==(`ETH_BURST_LENGTH-1))
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if(tx_burst_cnt==(`ETH_BURST_LENGTH-1))
|
begin
|
begin
|
tx_burst_en<= 1'b0;
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tx_burst_en<= 1'b0;
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`ifdef ETH_WISHBONE_B3
|
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m_wb_cti_o <= 3'b111;
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m_wb_cti_o <= 3'b111;
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`endif
|
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end
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end
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else
|
else
|
begin
|
begin
|
`ifdef ETH_WISHBONE_B3
|
|
m_wb_cti_o <= 3'b010;
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m_wb_cti_o <= 3'b010;
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`endif
|
|
end
|
end
|
end
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end
|
8'b00_?1_00_?1, // Idle and MWB needed
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8'b00_?1_00_?1, // Idle and MWB needed
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8'b01_?1_10_?1, // MWB continues
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8'b01_?1_10_?1, // MWB continues
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8'b01_01_01_01, // Clear (previously MW) and MWB needed
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8'b01_01_01_01, // Clear (previously MW) and MWB needed
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| Line 1211... |
Line 1199... |
m_wb_adr_o <= m_wb_adr_o+1'b1;
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m_wb_adr_o <= m_wb_adr_o+1'b1;
|
|
|
if(rx_burst_cnt==(`ETH_BURST_LENGTH-1))
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if(rx_burst_cnt==(`ETH_BURST_LENGTH-1))
|
begin
|
begin
|
rx_burst_en<= 1'b0;
|
rx_burst_en<= 1'b0;
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`ifdef ETH_WISHBONE_B3
|
|
m_wb_cti_o <= 3'b111;
|
m_wb_cti_o <= 3'b111;
|
`endif
|
|
end
|
end
|
else
|
else
|
begin
|
begin
|
`ifdef ETH_WISHBONE_B3
|
|
m_wb_cti_o <= 3'b010;
|
m_wb_cti_o <= 3'b010;
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`endif
|
|
end
|
end
|
end
|
end
|
8'b00_?1_00_?0 :// idle and MW is needed (data write to rx buffer)
|
8'b00_?1_00_?0 :// idle and MW is needed (data write to rx buffer)
|
begin
|
begin
|
MasterWbTX <= 1'b0;
|
MasterWbTX <= 1'b0;
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| Line 1284... |
Line 1268... |
IncrTxPointer<= 1'b0;
|
IncrTxPointer<= 1'b0;
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tx_burst_cnt<= 0;
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tx_burst_cnt<= 0;
|
tx_burst_en<= txfifo_cnt<(TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4));
|
tx_burst_en<= txfifo_cnt<(TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4));
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rx_burst_cnt<= 0;
|
rx_burst_cnt<= 0;
|
rx_burst_en<= MasterWbRX ? enough_data_in_rxfifo_for_burst_plus1 : enough_data_in_rxfifo_for_burst; // Counter is not decremented, yet, so plus1 is used.
|
rx_burst_en<= MasterWbRX ? enough_data_in_rxfifo_for_burst_plus1 : enough_data_in_rxfifo_for_burst; // Counter is not decremented, yet, so plus1 is used.
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`ifdef ETH_WISHBONE_B3
|
|
m_wb_cti_o <= 3'b0;
|
m_wb_cti_o <= 3'b0;
|
`endif
|
|
end
|
end
|
8'b??_00_10_00,// whatever and no master read or write is needed
|
8'b??_00_10_00,// whatever and no master read or write is needed
|
// (ack or err comes finishing previous access)
|
// (ack or err comes finishing previous access)
|
8'b??_00_01_00 : // Between cyc_cleared request was cleared
|
8'b??_00_01_00 : // Between cyc_cleared request was cleared
|
begin
|
begin
|
| Line 1301... |
Line 1283... |
IncrTxPointer<= 1'b0;
|
IncrTxPointer<= 1'b0;
|
rx_burst_cnt<= 0;
|
rx_burst_cnt<= 0;
|
// Counter is not decremented, yet, so plus1 is used.
|
// Counter is not decremented, yet, so plus1 is used.
|
rx_burst_en<= MasterWbRX ? enough_data_in_rxfifo_for_burst_plus1 :
|
rx_burst_en<= MasterWbRX ? enough_data_in_rxfifo_for_burst_plus1 :
|
enough_data_in_rxfifo_for_burst;
|
enough_data_in_rxfifo_for_burst;
|
`ifdef ETH_WISHBONE_B3
|
|
m_wb_cti_o <= 3'b0;
|
m_wb_cti_o <= 3'b0;
|
`endif
|
|
end
|
end
|
8'b00_00_00_00: // whatever and no master read or write is needed
|
8'b00_00_00_00: // whatever and no master read or write is needed
|
// (ack or err comes finishing previous access)
|
// (ack or err comes finishing previous access)
|
begin
|
begin
|
tx_burst_cnt<= 0;
|
tx_burst_cnt<= 0;
|
