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module Log2pipelined
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module Log2pipelined
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/*
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/*
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A fast base-2 logarithm function, 24 bits in, 8 bits out.
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A fast base-2 logarithm function, 24 bits (21 used) in, 8 bits out.
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Designed and coded by: Michael Dunn, http://www.cantares.on.ca/
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Designed and coded by: Michael Dunn, http://www.cantares.on.ca/
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(more info at the web site - see "Extras")
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(more info at the web site - see "Extras")
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Executes every cycle, with a latency of 3.
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Executes every cycle, with a latency of 3.
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This version has a smallish lookup table, hence, a slightly uneven output.
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Valid input range = 000100 - FFFFFF. In effect, there is a binary point:
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xxxx.yy. Logs of inputs below 1.00 are negative, and not handled by this design.
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License: Free to use & modify, but please keep this header intact.
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License: Free to use & modify, but please keep this header intact.
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July 18, 2010, Kitchener, Ontario, Canada
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July 22, 2010, Kitchener, Ontario, Canada
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This version not yet tested... In fact, has a problem. Stay tuned.
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*/
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*/
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(
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(
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input [23:0] DIN,
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input [23:0] DIN,
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input clk,
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input clk,
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reg [3:0] priencout1;
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reg [3:0] priencout1;
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reg [3:0] priencout2;
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reg [3:0] priencout2;
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reg [3:0] priencout3;
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reg [3:0] priencout3;
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reg [4:0] barrelout;
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reg [4:0] barrelout;
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reg [20:0] barrelin;
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reg [19:0] barrelin;
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reg [3:0] LUTout;
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reg [3:0] LUTout;
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assign DOUT = {priencout3, LUTout}; // Basic top-level connectivity
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always @(posedge clk) // Basic top-level connectivity
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always @(posedge clk)
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begin
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begin
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priencout2 <= priencout1;
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priencout2 <= priencout1;
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priencout3 <= priencout2;
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priencout3 <= priencout2;
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barrelin <= DIN[23:3];
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barrelin <= DIN[22:3];
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end
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end
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assign DOUT = {priencout3, LUTout};
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wire [20:0] tmp1 = (barrelin << ~priencout1);
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wire [19:0] tmp1 = (barrelin << ~priencout1); // Barrel shifter - OMG, it's a primitive in Verilog!
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always @(posedge clk) // Barrel shifter - OMG, it's a primitive in Verilog!
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always @(posedge clk)
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begin
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begin
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barrelout <= tmp1[19:15];
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barrelout <= tmp1[19:15];
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end
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end
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