`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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module positAddsub_tb_v;
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module positAddsub_tb_v;
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function [31:0] log2;
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function [31:0] log2;
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input reg [31:0] value;
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input reg [31:0] value;
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begin
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begin
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value = value-1;
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value = value-1;
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for (log2=0; value>0; log2=log2+1)
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for (log2=0; value>0; log2=log2+1)
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value = value>>1;
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value = value>>1;
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end
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end
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endfunction
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endfunction
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parameter N=52;
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parameter N=32;
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parameter E=8;
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parameter E=8;
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parameter Bs=log2(N);
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parameter Bs=log2(N);
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parameter es = 4;
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parameter es = 2;
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reg [N-1:0] in;
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reg [N-1:0] in;
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reg clk;
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reg clk;
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reg [5:0] cnt;
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reg [5:0] cnt;
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wire [N-1:0] out, out2, out3;
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wire [N-1:0] out, out2, out3;
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reg [N-1:0] a1, b1;
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reg [N-1:0] a1, b1;
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wire [N-1:0] a, b;
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wire [N-1:0] a, b;
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wire [N-1:0] psum, fsum, fa, fb, ad, bd, psumd, out2d, psum1;
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wire [N-1:0] psum, fsum, fa, fb, ad, bd, psumd, out2d, psum1;
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// Instantiate the Unit Under Test (UUT)
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// Instantiate the Unit Under Test (UUT)
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intToPosit #(.PSTWID(N), .es(es)) u1a (.i(a1), .o(a));
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intToPosit #(.PSTWID(N), .es(es)) u1a (.i(a1), .o(a));
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intToPosit #(.PSTWID(N), .es(es)) u1b (.i(b1), .o(b));
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intToPosit #(.PSTWID(N), .es(es)) u1b (.i(b1), .o(b));
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positToFp #(.FPWID(N), .PSTWID(N), .es(es)) u2
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/*
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(
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positToFp #(.FPWID(N), .PSTWID(N), .es(es)) u2
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.i(a),
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(
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.o(fa)
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.i(a),
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);
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.o(fa)
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);
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positToFp #(.FPWID(N), .PSTWID(N), .es(es)) u3
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(
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positToFp #(.FPWID(N), .PSTWID(N), .es(es)) u3
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.i(b),
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(
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.o(fb)
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.i(b),
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);
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.o(fb)
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);
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positAddsub #(.PSTWID(N), .es(es)) uadd1 (1'b0,a,b,psum);
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*/
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fpAddsub #(.FPWID(N)) uadd2 (clk,1'b1,3'd0,1'b0,fa,fb,fsum);
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positAddsub #(.PSTWID(N), .es(es)) uadd1 (1'b0,a1,b1,psum);
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posit_add #(.N(N),.es(es)) uadd3 (a, b, 1'b1, psum1);
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//fpAddsub #(.FPWID(N)) uadd2 (clk,1'b1,3'd0,1'b0,fa,fb,fsum);
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posit_add #(.N(N),.es(es)) uadd3 (a1, b1, 1'b1, psum1);
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positToFp #(.FPWID(N), .PSTWID(N), .es(es)) u4
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/*
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(
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positToFp #(.FPWID(N), .PSTWID(N), .es(es)) u4
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.i(psum),
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(
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.o(out2)
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.i(psum),
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);
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.o(out2)
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);
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*/
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delay2 #(N) ud1 (.i(a), .o(ad));
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delay2 #(N) ud1 (.i(a), .o(ad));
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delay2 #(N) ud2 (.i(a), .o(bd));
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delay2 #(N) ud2 (.i(a), .o(bd));
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delay2 #(N) ud3 (.i(psum), .o(psumd));
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delay2 #(N) ud3 (.i(psum), .o(psumd));
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delay2 #(N) ud4 (.i(out2), .o(out2d));
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delay2 #(N) ud4 (.i(out2), .o(out2d));
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//FP_to_posit #(.N(32), .E(8), .es(es)) u3 (in, out3);
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//FP_to_posit #(.N(32), .E(8), .es(es)) u3 (in, out3);
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//Posit_to_FP #(.N(32), .E(8), .es(es)) u5 (out, out3);
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//Posit_to_FP #(.N(32), .E(8), .es(es)) u5 (out, out3);
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initial begin
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initial begin
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a1 = $urandom(1);
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a1 = $urandom(1);
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b1 = $urandom(2);
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b1 = $urandom(2);
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cnt = 0;
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cnt = 0;
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// Initialize Inputs
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// Initialize Inputs
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clk = 1;
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clk = 1;
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// Wait 100 ns for global reset to finish
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// Wait 100 ns for global reset to finish
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#101 in = 32'h0080ffff;
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#101 in = 32'h0080ffff;
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#325150
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#325150
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$fclose(outfile);
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$fclose(outfile);
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$finish;
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$finish;
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end
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end
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// 23acc3ec 2d37240c 230d8602 630d8602*
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// 343b2e06 6c4e8633 6c5194ff 6c5194fe*
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always #5 clk=~clk;
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always #5 clk=~clk;
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always @(posedge clk) begin
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always @(posedge clk) begin
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cnt = cnt + 1;
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cnt = cnt + 1;
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case(cnt)
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case(cnt)
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0:
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0:
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begin
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begin
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a1 = 0;
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a1 = 0;
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b1 = 0;
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b1 = 0;
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end
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end
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1:
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1:
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begin
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begin
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a1 = 0;
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a1 = 0;
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b1 = 10;
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b1 = 10;
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end
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end
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2:
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2:
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begin
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begin
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a1 = 10;
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a1 = 32'h23acc3ec;
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b1 = 10;
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b1 = 32'h2d37240c;
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end
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3:
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begin
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a1 = 32'h343b2e06;
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b1 = 32'h6c4e8633;
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end
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end
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default:
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default:
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begin
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begin
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a1 = $urandom();
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a1 = $urandom();
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b1 = $urandom();
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b1 = $urandom();
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end
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end
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endcase
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endcase
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end
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end
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integer outfile;
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integer outfile;
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initial outfile = $fopen("d:/cores5/Gambit/v5/rtl/cpu/fpu/test_bench/positAddsub_tvo32.txt", "wb");
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initial outfile = $fopen("d:/cores2020/rtf64/v2/rtl/verilog/cpu/pau/test_bench/positAddsub_tvo32.txt", "wb");
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always @(negedge clk) begin
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always @(negedge clk) begin
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$fwrite(outfile, "%h\t%h\t%h\t%h\n",a,b,psum,psum1);
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$fwrite(outfile, "%h\t%h\t%h\t%h%c\n",a1,b1,psum,psum1,psum!=psum1?"*":" ");
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end
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end
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endmodule
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endmodule
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