// ============================================================================
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// ============================================================================
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// __
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// __
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// \\__/ o\ (C) 2020 Robert Finch, Waterloo
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// \\__/ o\ (C) 2020 Robert Finch, Waterloo
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// \ __ / All rights reserved.
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// \ __ / All rights reserved.
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// \/_// robfinch@finitron.ca
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// \/_// robfinch@finitron.ca
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// ||
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// ||
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//
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//
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// intToPosit.sv
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// intToPosit.sv
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// - integer to posit number converter
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// - integer to posit number converter
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// - parameterized width
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// - parameterized width
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//
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//
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//
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//
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// This source file is free software: you can redistribute it and/or modify
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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// (at your option) any later version.
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//
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//
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// This source file is distributed in the hope that it will be useful,
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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// GNU General Public License for more details.
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//
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//
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// You should have received a copy of the GNU General Public License
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see .
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// along with this program. If not, see .
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//
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//
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// ============================================================================
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// ============================================================================
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`include "positConfig.sv"
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`include "positConfig.sv"
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module intToPosit(i, o);
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module intToPosit(i, o);
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`include "positSize.sv"
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`include "positSize.sv"
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localparam rs = $clog2(PSTWID-1);
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localparam rs = $clog2(PSTWID-1);
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localparam lzs = $clog2(PSTWID-2);
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localparam lzs = $clog2(PSTWID-1)-1;
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input [PSTWID-1:0] i;
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input [PSTWID-1:0] i;
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output [PSTWID-1:0] o;
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output [PSTWID-1:0] o;
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wire [PSTWID*2-1+es+3-2:0] tmp, tmp1;
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wire [PSTWID*2-1+es+3-2:0] tmp, tmp1;
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wire [PSTWID-2:0] ii = i[PSTWID-1] ? -i : i;
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wire [PSTWID-2:0] ii = i[PSTWID-1] ? -i : i;
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wire [lzs:0] lzcnt;
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wire [lzs:0] lzcnt;
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wire [PSTWID-1:0] rnd_ulp, tmp2, tmp2_rnd_ulp;
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wire [PSTWID-1:0] rnd_ulp, tmp2, tmp2_rnd_ulp;
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integer n;
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integer n;
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positCntlz #(.PSTWID(PSTWID)) u1 (.i(ii[PSTWID-2:0]), .o(lzcnt));
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positCntlz #(.PSTWID(PSTWID)) u1 (.i(ii[PSTWID-2:0]), .o(lzcnt));
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wire sgn = i[PSTWID-1];
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wire sgn = i[PSTWID-1];
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wire [rs:0] rgm = (PSTWID - (lzcnt + 2)) >> es;
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wire [rs:0] rgm = (PSTWID - (lzcnt + 2)) >> es;
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wire [PSTWID-3:0] sig = ii << lzcnt; // left align significand, chop off leading one
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wire [PSTWID-3:0] sig = ii << lzcnt; // left align significand, chop off leading one
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generate begin : gExpandedPosit
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generate begin : gExpandedPosit
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// The number is represented as 1.x so for an integer it
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// The number is represented as 1.x so for an integer it
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// always needs to be left shifted.
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// always needs to be left shifted.
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// Add three trailers for guard, round and sticky.
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// Add three trailers for guard, round and sticky.
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if (es > 0) begin
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if (es > 0) begin
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// exp = lzcnt mod (2**es)
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// exp = lzcnt mod (2**es)
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// remember es is constant so there are no shifts really
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// remember es is constant so there are no shifts really
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wire [es-1:0] exp = (PSTWID - (lzcnt + 2)) & {es{1'b1}};
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wire [es-1:0] exp = (PSTWID - (lzcnt + 2)) & {es{1'b1}};
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assign tmp = {{{PSTWID-1{1'b1}},1'b0},exp,sig,3'b0};
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assign tmp = {{{PSTWID-1{1'b1}},1'b0},exp,sig,3'b0};
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end
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end
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else
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else
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assign tmp = {{{PSTWID-1{1'b1}},1'b0},sig,3'b0};
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assign tmp = {{{PSTWID-1{1'b1}},1'b0},sig,3'b0};
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end
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end
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endgenerate
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endgenerate
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// Compute regime shift amount = number of bits to represent regime
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// Compute regime shift amount = number of bits to represent regime
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// Need one extra bit for the terminator, and one extra '1' bit.
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// Need one extra bit for the terminator, and one extra '1' bit.
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wire [rs:0] rgm_sh = rgm + 2'd2;
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wire [rs:0] rgm_sh = rgm + 2'd2;
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assign tmp1 = tmp >> rgm_sh;
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assign tmp1 = tmp >> rgm_sh;
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wire L = tmp[rgm_sh-0+es];
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wire L = tmp[rgm_sh-0+es];
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wire G = tmp[rgm_sh-1+es];
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wire G = tmp[rgm_sh-1+es];
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wire R = tmp[rgm_sh-2+es];
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wire R = tmp[rgm_sh-2+es];
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reg S;
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reg S;
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wire ulp;
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wire ulp;
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always @*
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always @*
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begin
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begin
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S = 0;
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S = 0;
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for (n = 0; n < PSTWID; n = n + 1) begin
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for (n = 0; n < PSTWID; n = n + 1) begin
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if (n < rgm_sh - 2 + es)
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if (n < rgm_sh - 2 + es)
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S = S | tmp[n];
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S = S | tmp[n];
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end
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end
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end
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end
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// Extract the bits representing the number, note leave off sign bit
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// Extract the bits representing the number, note leave off sign bit
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assign tmp2 = tmp1[PSTWID-3+es+3:es+2];
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assign tmp2 = tmp1[PSTWID-3+es+3:es+2];
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// Round
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// Round
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assign ulp = ((G & (R | S)) | (L & G & ~(R | S)));
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assign ulp = ((G & (R | S)) | (L & G & ~(R | S)));
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assign rnd_ulp = {{PSTWID-1{1'b0}},ulp};
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assign rnd_ulp = {{PSTWID-1{1'b0}},ulp};
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assign tmp2_rnd_ulp = tmp2 + rnd_ulp;
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assign tmp2_rnd_ulp = tmp2 + rnd_ulp;
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// Final output
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// Final output
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assign o = i=={PSTWID{1'b0}} ? {PSTWID{1'b0}} : sgn ? -tmp2_rnd_ulp : tmp2_rnd_ulp;
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assign o = i=={PSTWID{1'b0}} ? {PSTWID{1'b0}} : sgn ? -tmp2_rnd_ulp : tmp2_rnd_ulp;
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endmodule
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endmodule
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